From patchwork Wed Sep 12 18:32:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Agner X-Patchwork-Id: 10598139 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A664214E5 for ; Wed, 12 Sep 2018 18:32:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9A07C22B26 for ; Wed, 12 Sep 2018 18:32:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8C3B42AA60; Wed, 12 Sep 2018 18:32:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2F66D2AA44 for ; Wed, 12 Sep 2018 18:32:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1CD866E5C1; Wed, 12 Sep 2018 18:32:48 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.kmu-office.ch (mail.kmu-office.ch [IPv6:2a02:418:6a02::a2]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6A32E6E5C1 for ; Wed, 12 Sep 2018 18:32:46 +0000 (UTC) Received: from trochilidae.toradex.int (75-146-58-181-Washington.hfc.comcastbusiness.net [75.146.58.181]) by mail.kmu-office.ch (Postfix) with ESMTPSA id AF8265C1D59; Wed, 12 Sep 2018 20:32:40 +0200 (CEST) From: Stefan Agner To: linus.walleij@linaro.org, Laurent.pinchart@ideasonboard.com, airlied@linux.ie, robh+dt@kernel.org, mark.rutland@arm.com, shawnguo@kernel.org, s.hauer@pengutronix.de, p.zabel@pengutronix.de Subject: [PATCH v2 3/8] drm/bridge: simplify bridge timing info Date: Wed, 12 Sep 2018 11:32:17 -0700 Message-Id: <20180912183222.25414-4-stefan@agner.ch> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180912183222.25414-1-stefan@agner.ch> References: <20180912183222.25414-1-stefan@agner.ch> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, max.krummenacher@toradex.com, marcel.ziswiler@toradex.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-imx@nxp.com, kernel@pengutronix.de, fabio.estevam@nxp.com, sean@poorly.run, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Bridges are typically connected to a parallel display signal with pixel clock, sync signals and data lines. Parallel display signals are also used in lower-end embedded display panels. For parallel display panels we currently do not specify setup/hold times. From discussions on the mailing list it seems not convincing that this is currently really required for bridges either. Remove setup/hold timings again to better align timing information of displays and briges. Signed-off-by: Stefan Agner --- drivers/gpu/drm/bridge/dumb-vga-dac.c | 17 +++++------------ include/drm/drm_bridge.h | 14 -------------- 2 files changed, 5 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/bridge/dumb-vga-dac.c b/drivers/gpu/drm/bridge/dumb-vga-dac.c index d5aa0f931ef2..b2309ad228cf 100644 --- a/drivers/gpu/drm/bridge/dumb-vga-dac.c +++ b/drivers/gpu/drm/bridge/dumb-vga-dac.c @@ -229,14 +229,14 @@ static int dumb_vga_remove(struct platform_device *pdev) /* * We assume the ADV7123 DAC is the "default" for historical reasons * Information taken from the ADV7123 datasheet, revision D. - * NOTE: the ADV7123EP seems to have other timings and need a new timings - * set if used. */ static const struct drm_bridge_timings default_dac_timings = { - /* Timing specifications, datasheet page 7 */ + /* + * From Timing diagram, datasheet page 7. The bridge samples + * on pixel clocks positive edge, hence the display controller + * should drive signals on the negative edge. + */ .input_bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE, - .setup_time_ps = 500, - .hold_time_ps = 1500, }; /* @@ -246,10 +246,6 @@ static const struct drm_bridge_timings default_dac_timings = { static const struct drm_bridge_timings ti_ths8134_dac_timings = { /* From timing diagram, datasheet page 9 */ .input_bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE, - /* From datasheet, page 12 */ - .setup_time_ps = 3000, - /* I guess this means latched input */ - .hold_time_ps = 0, }; /* @@ -259,9 +255,6 @@ static const struct drm_bridge_timings ti_ths8134_dac_timings = { static const struct drm_bridge_timings ti_ths8135_dac_timings = { /* From timing diagram, datasheet page 14 */ .input_bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE, - /* From datasheet, page 16 */ - .setup_time_ps = 2000, - .hold_time_ps = 500, }; static const struct of_device_id dumb_vga_match[] = { diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h index 45e90f4b46c3..1a1d08350eaf 100644 --- a/include/drm/drm_bridge.h +++ b/include/drm/drm_bridge.h @@ -251,20 +251,6 @@ struct drm_bridge_timings { * &drm_display_info->bus_flags. */ u32 input_bus_flags; - /** - * @setup_time_ps: - * - * Defines the time in picoseconds the input data lines must be - * stable before the clock edge. - */ - u32 setup_time_ps; - /** - * @hold_time_ps: - * - * Defines the time in picoseconds taken for the bridge to sample the - * input signal after the clock edge. - */ - u32 hold_time_ps; }; /**