| Message ID | 20180928180403.22499-1-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/5] drm/dp/mst: Configure no_stop_bit correctly for remote i2c xfers | expand |
On Fri, 2018-09-28 at 21:03 +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > We aren't supposed to force a stop+start between every i2c msg > when performing multi message transfers. This should eg. cause > the DDC segment address to be reset back to 0 between writing > the segment address and reading the actual EDID extension block. > > To quote the E-DDC spec: > "... this standard requires that the segment pointer be > reset to 00h when a NO ACK or a STOP condition is received." Related question, do you know why the segment and ddc addresses are defined as 0x30 and 0x50? The E-DDC spec says they should be at 0x60 and 0xA0/0xA1. > > Since we're going to touch this might as well consult the > I2C_M_STOP flag to determine whether we want to force the stop > or not. Reviewing this took a lot of spec reading than I expected. Setting the no_stop_bit after writing the segment address makes sense. I have one concern though. drm_do_probe_ddc_edid does not make use of the I2C_M_STOP flag, which in turn means we won't reset the no_stop_bit at the end of edid read. Pass the i2c stop flag from the caller? > > Cc: Brian Vincent <brainn@gmail.com> > References: https://bugs.freedesktop.org/show_bug.cgi?id=108081 > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c > b/drivers/gpu/drm/drm_dp_mst_topology.c > index 5ff1d79b86c4..3b400eab18a2 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -3276,6 +3276,7 @@ static int drm_dp_mst_i2c_xfer(struct > i2c_adapter *adapter, struct i2c_msg *msgs > msg.u.i2c_read.transactions[i].i2c_dev_id = > msgs[i].addr; > msg.u.i2c_read.transactions[i].num_bytes = msgs[i].len; > msg.u.i2c_read.transactions[i].bytes = msgs[i].buf; > + msg.u.i2c_read.transactions[i].no_stop_bit = > !(msgs[i].flags & I2C_M_STOP); > } > msg.u.i2c_read.read_i2c_device_id = msgs[num - 1].addr; > msg.u.i2c_read.num_bytes_read = msgs[num - 1].len;
On Fri, 2018-12-07 at 12:45 -0800, Dhinakaran Pandiyan wrote: > On Fri, 2018-09-28 at 21:03 +0300, Ville Syrjala wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > We aren't supposed to force a stop+start between every i2c msg > > when performing multi message transfers. This should eg. cause > > the DDC segment address to be reset back to 0 between writing > > the segment address and reading the actual EDID extension block. > > > > To quote the E-DDC spec: > > "... this standard requires that the segment pointer be > > reset to 00h when a NO ACK or a STOP condition is received." > > Related question, do you know why the segment and ddc addresses are > defined as 0x30 and 0x50? The E-DDC spec says they should be at 0x60 > and 0xA0/0xA1. > > > > > Since we're going to touch this might as well consult the > > I2C_M_STOP flag to determine whether we want to force the stop > > or not. > > Reviewing this took a lot of spec reading than I expected. > > Setting the no_stop_bit after writing the segment address makes > sense. > I have one concern though. drm_do_probe_ddc_edid does not make use of > the I2C_M_STOP flag, which in turn means we won't reset the > no_stop_bit > at the end of edid read. Pass the i2c stop flag from the caller? > Never mind, the no_stop_bit is relevant only between i2c writes. Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > > > Cc: Brian Vincent <brainn@gmail.com> > > References: https://bugs.freedesktop.org/show_bug.cgi?id=108081 > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/drm_dp_mst_topology.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c > > b/drivers/gpu/drm/drm_dp_mst_topology.c > > index 5ff1d79b86c4..3b400eab18a2 100644 > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > > @@ -3276,6 +3276,7 @@ static int drm_dp_mst_i2c_xfer(struct > > i2c_adapter *adapter, struct i2c_msg *msgs > > msg.u.i2c_read.transactions[i].i2c_dev_id = > > msgs[i].addr; > > msg.u.i2c_read.transactions[i].num_bytes = msgs[i].len; > > msg.u.i2c_read.transactions[i].bytes = msgs[i].buf; > > + msg.u.i2c_read.transactions[i].no_stop_bit = > > !(msgs[i].flags & I2C_M_STOP); > > } > > msg.u.i2c_read.read_i2c_device_id = msgs[num - 1].addr; > > msg.u.i2c_read.num_bytes_read = msgs[num - 1].len;
On Fri, Dec 07, 2018 at 12:45:25PM -0800, Dhinakaran Pandiyan wrote: > On Fri, 2018-09-28 at 21:03 +0300, Ville Syrjala wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > We aren't supposed to force a stop+start between every i2c msg > > when performing multi message transfers. This should eg. cause > > the DDC segment address to be reset back to 0 between writing > > the segment address and reading the actual EDID extension block. > > > > To quote the E-DDC spec: > > "... this standard requires that the segment pointer be > > reset to 00h when a NO ACK or a STOP condition is received." > Related question, do you know why the segment and ddc addresses are > defined as 0x30 and 0x50? The E-DDC spec says they should be at 0x60 > and 0xA0/0xA1. The spec uses 'slave_address << 1 | r/w'.
On Mon, 2018-12-10 at 18:39 +0200, Ville Syrjälä wrote: > On Fri, Dec 07, 2018 at 12:45:25PM -0800, Dhinakaran Pandiyan wrote: > > On Fri, 2018-09-28 at 21:03 +0300, Ville Syrjala wrote: > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > > > We aren't supposed to force a stop+start between every i2c msg > > > when performing multi message transfers. This should eg. cause > > > the DDC segment address to be reset back to 0 between writing > > > the segment address and reading the actual EDID extension block. > > > > > > To quote the E-DDC spec: > > > "... this standard requires that the segment pointer be > > > reset to 00h when a NO ACK or a STOP condition is received." > > > > Related question, do you know why the segment and ddc addresses are > > defined as 0x30 and 0x50? The E-DDC spec says they should be at > > 0x60 > > and 0xA0/0xA1. > > The spec uses 'slave_address << 1 | r/w'. Got it, thanks. -DK
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 5ff1d79b86c4..3b400eab18a2 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -3276,6 +3276,7 @@ static int drm_dp_mst_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs msg.u.i2c_read.transactions[i].i2c_dev_id = msgs[i].addr; msg.u.i2c_read.transactions[i].num_bytes = msgs[i].len; msg.u.i2c_read.transactions[i].bytes = msgs[i].buf; + msg.u.i2c_read.transactions[i].no_stop_bit = !(msgs[i].flags & I2C_M_STOP); } msg.u.i2c_read.read_i2c_device_id = msgs[num - 1].addr; msg.u.i2c_read.num_bytes_read = msgs[num - 1].len;