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Wed, 3 Oct 2018 09:40:57 +0000 (GMT) From: Christoph Manszewski To: dri-devel@lists.freedesktop.org Subject: [PATCH 1/2] drm/exynos: decon: Make plane alpha configurable Date: Wed, 3 Oct 2018 11:40:43 +0200 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538559644-30269-1-git-send-email-c.manszewski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRjm27m6Whyn4NeFVdOuYMsu+EFXoeJkP7LoRpZ5qoNmzmRTKyHS IvGSc2mi2Zi67nNpzqVzWeIyh4QbaUUpZtF+mJe0pkaRltvp8u95n8v3vLx8NCZ1EXPoE0kp vCqJS5STYry+7bsztEpjiV5pfkqi7mongfKd7SJUW1pDIMejWwC9HB8hUeN7G4UK+7Q46n/3 AkcFHwcx5HI9oFDHhSEKmT++JlCXTUeiUtcTESqwthDofmsvhSq/PMRRb1ErQKVFn8jNAaxJ bwKs2ZhDsg0T7wlW376L7ctziNi6m+fZxsLHItZh66ZYjcUIWI9ZFiU+KF5/nE88kcarFBtj xfHXrZlEcrbsTHuRlsoAxtm5gKYhswbevLotF4hpKXMXwLaBfFIYxgBsassjhMED4I+ePCwX +PkSuuIuIAh3ABztdhP/Is5nWsrrIpm1sKf3K+nFgUwwnLxi9CUwpouALkMl7hUCmK0wo20K 9y6CM4tgg3mJ0CCDb505vjY/Zjs02W2+AsgMU9B9LdsnSJg0WKYZJYXAFqgZNYoEHAAHHBZK wPPgr8ZykRC+CGD32Os/L2kBbKnKxQXXOmh+MyDyboExy2CNTSHQEdBtqAfClWbBN8P+Xhqb hoX1JZhAS2B2llRwL4aDFgv5t7bfMw4EzMKSn3pMOJAOwKK+alIL5pf9L6sAwAiC+FS1Mo5X hyXxp1eoOaU6NSluxbFTSjOY/mbPpxxfrWC886gdMDSQz5RYK+uipQSXpj6rtANIY/JAiYab piTHubPpvOrUEVVqIq+2g7k0Lg+S3NbXRkuZOC6FP8nzybzqryqi/eZkAI6ef+CbrCOmVZse bq26vCFjsmNT7SHGvF88GZr5Oa6HL3duPNfcHLrPHVabXLDn4YzAkCfjI0cid8TGxC+8sca0 uvPDpb2HpUvvVRhm7Ov3k3kiF0wkfDME++sUQ+nrm1Y2NCt2Pn1lUqpKf1KKuojirN3pCbtj lOF4i+5VUFTIKjmujufClmMqNfcbM+QuxWIDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrAIsWRmVeSWpSXmKPExsVy+t/xu7qr+rZEG9y8ymVxa905VovecyeZ LDbOWM9qcXz3UkaLK1/fs1nsfLCL3WLS/QksFi/uXWSx6H/8mtni/PkN7BZnm96wW2x6fI3V 4vKuOWwWM87vY7Lo33GQ1WLtkbvsFgs/bmWxuDv5CKPFjMkv2RyEPdbMW8PosWlVJ5vH9m8P WD3mnQz0uN99nMlj85J6j52T9jJ5HN91i92jb8sqRo/Pm+QCuKL0bIryS0tSFTLyi0tslaIN LYz0DC0t9IxMLPUMjc1jrYxMlfTtbFJSczLLUov07RL0MmbvaGQt6JCrODl5AnsD4yrJLkZO DgkBE4k5Uy8zdjFycQgJLGWUmD77OzNEQkZi3tk+NghbWOLPtS42iKJPjBJnTuwGK2ITMJW4 ffcTWJGIgLLE34mrwCYxCzxklXi/sBMsISzgKtFw7B9LFyMHB4uAqsT2TeogYV4BD4mN206x QCyQk7h5rhNsJqeAp8SaQ7tYQWwhoJqvvzYwTmDkW8DIsIpRJLW0ODc9t9hIrzgxt7g0L10v OT93EyMwtrYd+7llB2PXu+BDjAIcjEo8vAnzN0cLsSaWFVfmHmKU4GBWEuHtSwQK8aYkVlal FuXHF5XmpBYfYjQFumkis5Rocj4w7vNK4g1NDc0tLA3Njc2NzSyUxHnPG1RGCQmkJ5akZqem FqQWwfQxcXBKNTBy/DMJydt+/iSnA6v1PYl9V9qni9/Q2OGWpZzucCPeZpXovJpH1+8sk5N4 a/c85e8q0V/fnlXL/HPs0UuSkVQIWWLtIln6+saCHTLmPrumndli/+ZE3LWqD5HXXyy8+n5P +ulcyZYJLpwS66X3Wt7fGS7DnuQkttT2mNw3IYPz96Rs9uncKrVXYinOSDTUYi4qTgQAbjYu cMMCAAA= Message-Id: <20181003094058eucas1p10dba450852a4ce8dc521b15e63ebabfa~aD9ubxJ5A1867918679eucas1p1K@eucas1p1.samsung.com> X-CMS-MailID: 20181003094058eucas1p10dba450852a4ce8dc521b15e63ebabfa X-Msg-Generator: CA X-RootMTR: 20181003094058eucas1p10dba450852a4ce8dc521b15e63ebabfa X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20181003094058eucas1p10dba450852a4ce8dc521b15e63ebabfa References: <1538559644-30269-1-git-send-email-c.manszewski@samsung.com> X-Mailman-Approved-At: Thu, 04 Oct 2018 07:14:20 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-samsung-soc@vger.kernel.org, Bartlomiej Zolnierkiewicz , Christoph Manszewski , Seung-Woo Kim , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , David Airlie , Kyungmin Park , Kukjin Kim , Lowry Li , Sean Paul , linux-arm-kernel@lists.infradead.org, Marek Szyprowski MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The decon hardware supports variable plane alpha. Currently planes are opaque, make this configurable. Tested on TM2 with Exynos 5433 CPU, on top of exynos-drm-next. Signed-off-by: Christoph Manszewski --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 30 +++++++++++++++++++++++++++ drivers/gpu/drm/exynos/regs-decon5433.h | 4 ++++ 2 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index 94529aa82339..dff540160199 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -84,6 +84,14 @@ static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR, }; +static const unsigned int capabilities[WINDOWS_NR] = { + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, +}; + static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, u32 val) { @@ -259,6 +267,24 @@ static void decon_commit(struct exynos_drm_crtc *crtc) decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); } +static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win, + struct drm_framebuffer *fb) +{ + struct exynos_drm_plane plane = ctx->planes[win]; + struct exynos_drm_plane_state *state = + to_exynos_plane_state(plane.base.state); + unsigned int alpha = state->base.alpha; + u32 win_alpha = alpha >> 8; + u32 val = 0; + + if (alpha != DRM_BLEND_ALPHA_OPAQUE) { + val = VIDOSD_Wx_ALPHA_R_F(win_alpha) | VIDOSD_Wx_ALPHA_G_F(win_alpha) | + VIDOSD_Wx_ALPHA_B_F(win_alpha); + decon_set_bits(ctx, DECON_VIDOSDxC(win), 0xffffff, val); + decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW); + } +} + static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, struct drm_framebuffer *fb) { @@ -267,6 +293,8 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, val = readl(ctx->addr + DECON_WINCONx(win)); val &= WINCONx_ENWIN_F; + decon_win_set_bldmod(ctx, win, fb); + switch (fb->format->format) { case DRM_FORMAT_XRGB1555: val |= WINCONx_BPPMODE_16BPP_I1555; @@ -288,6 +316,7 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, val |= WINCONx_BPPMODE_32BPP_A8888; val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F; val |= WINCONx_BURSTLEN_16WORD; + val |= WINCONx_ALPHA_MUL_F; break; } @@ -561,6 +590,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data) ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); ctx->configs[win].zpos = win - ctx->first_win; ctx->configs[win].type = decon_win_types[win]; + ctx->configs[win].capabilities = capabilities[win]; ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, &ctx->configs[win]); diff --git a/drivers/gpu/drm/exynos/regs-decon5433.h b/drivers/gpu/drm/exynos/regs-decon5433.h index 19ad9e47945e..f42d8f0adf5d 100644 --- a/drivers/gpu/drm/exynos/regs-decon5433.h +++ b/drivers/gpu/drm/exynos/regs-decon5433.h @@ -104,6 +104,7 @@ #define WINCONx_BURSTLEN_16WORD (0x0 << 10) #define WINCONx_BURSTLEN_8WORD (0x1 << 10) #define WINCONx_BURSTLEN_4WORD (0x2 << 10) +#define WINCONx_ALPHA_MUL_F (1 << 7) #define WINCONx_BLD_PIX_F (1 << 6) #define WINCONx_BPPMODE_MASK (0xf << 2) #define WINCONx_BPPMODE_16BPP_565 (0x5 << 2) @@ -206,4 +207,7 @@ #define CRCCTRL_CRCEN (0x1 << 0) #define CRCCTRL_MASK (0x7) +/* BLENDCON */ +#define BLEND_NEW (1 << 0) + #endif /* EXYNOS_REGS_DECON5433_H */