diff mbox series

[v5,24/28] drm/i915/dp: Configure Display stream splitter registers during DSC enable

Message ID 20181005232306.31133-25-manasi.d.navare@intel.com (mailing list archive)
State New, archived
Headers show
Series Display Stream Compression enabling on eDP/DP | expand

Commit Message

Navare, Manasi Oct. 5, 2018, 11:23 p.m. UTC 
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.

v2:
* Rebase (Manasi)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intelcom>
---
 drivers/gpu/drm/i915/intel_vdsc.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

Comments

Ville Syrjala Oct. 18, 2018, 5:02 p.m. UTC | #1 
On Fri, Oct 05, 2018 at 04:23:02PM -0700, Manasi Navare wrote:
> Display Stream Splitter registers need to be programmed to enable
> the joiner if two DSC engines are used and also to enable
> the left and the right DSC engines. This happens as part of
> the DSC enabling routine in the source in atomic commit.
> 
> v2:
> * Rebase (Manasi)
> 
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intelcom>
> ---
>  drivers/gpu/drm/i915/intel_vdsc.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> index f2b3b30b6f5e..d3001647a887 100644
> --- a/drivers/gpu/drm/i915/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -1009,6 +1009,12 @@ static void intel_dp_send_dsc_pps_sdp(struct intel_encoder *encoder,
>  void intel_dsc_enable(struct intel_encoder *encoder,
>  		      struct intel_crtc_state *crtc_state)
>  {
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	enum pipe pipe = crtc->pipe;
> +	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> +	u32 dss_ctl1_val = 0;
> +	u32 dss_ctl2_val = 0;
>  
>  	if (!crtc_state->dsc_params.compression_enable)
>  		return;
> @@ -1017,5 +1023,21 @@ void intel_dsc_enable(struct intel_encoder *encoder,
>  
>  	intel_dp_send_dsc_pps_sdp(encoder, crtc_state);
>  
> +	/* Configure DSS_CTL registers for DSC */
> +	if (encoder->type == INTEL_OUTPUT_EDP) {

Presumably this should check the transcoder instead? I see a lot of
similar confusion in other patches as well.

> +		dss_ctl1_reg = DSS_CTL1;
> +		dss_ctl2_reg = DSS_CTL2;
> +	} else {
> +		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
> +		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
> +	}
> +	dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
> +	if (crtc_state->dsc_params.dsc_split) {
> +		dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
> +		dss_ctl1_val |= JOINER_ENABLE;
> +	}
> +	I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
> +	I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
> +
>  	return;
>  }
> -- 
> 2.18.0
Navare, Manasi Oct. 19, 2018, 10:40 p.m. UTC | #2 
On Thu, Oct 18, 2018 at 08:02:14PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 05, 2018 at 04:23:02PM -0700, Manasi Navare wrote:
> > Display Stream Splitter registers need to be programmed to enable
> > the joiner if two DSC engines are used and also to enable
> > the left and the right DSC engines. This happens as part of
> > the DSC enabling routine in the source in atomic commit.
> > 
> > v2:
> > * Rebase (Manasi)
> > 
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intelcom>
> > ---
> >  drivers/gpu/drm/i915/intel_vdsc.c | 22 ++++++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> > index f2b3b30b6f5e..d3001647a887 100644
> > --- a/drivers/gpu/drm/i915/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> > @@ -1009,6 +1009,12 @@ static void intel_dp_send_dsc_pps_sdp(struct intel_encoder *encoder,
> >  void intel_dsc_enable(struct intel_encoder *encoder,
> >  		      struct intel_crtc_state *crtc_state)
> >  {
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	enum pipe pipe = crtc->pipe;
> > +	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> > +	u32 dss_ctl1_val = 0;
> > +	u32 dss_ctl2_val = 0;
> >  
> >  	if (!crtc_state->dsc_params.compression_enable)
> >  		return;
> > @@ -1017,5 +1023,21 @@ void intel_dsc_enable(struct intel_encoder *encoder,
> >  
> >  	intel_dp_send_dsc_pps_sdp(encoder, crtc_state);
> >  
> > +	/* Configure DSS_CTL registers for DSC */
> > +	if (encoder->type == INTEL_OUTPUT_EDP) {
> 
> Presumably this should check the transcoder instead? I see a lot of
> similar confusion in other patches as well.
>

So that would mean that if we force eDP output on pipe B then it will use transcoder B
and hence DSC engines on transcoder B, so we would use the DSS_CTL1/2 only for
Transcoder EDP else it shd use ICL_PIPE_DSS_CTL1(pipe).

And same for the DSC PPS configure patch as well.

Correct?
 
> > +		dss_ctl1_reg = DSS_CTL1;
> > +		dss_ctl2_reg = DSS_CTL2;
> > +	} else {
> > +		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
> > +		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
> > +	}
> > +	dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
> > +	if (crtc_state->dsc_params.dsc_split) {
> > +		dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
> > +		dss_ctl1_val |= JOINER_ENABLE;
> > +	}
> > +	I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
> > +	I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
> > +
> >  	return;
> >  }
> > -- 
> > 2.18.0
> 
> -- 
> Ville Syrjälä
> Intel
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index f2b3b30b6f5e..d3001647a887 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1009,6 +1009,12 @@  static void intel_dp_send_dsc_pps_sdp(struct intel_encoder *encoder,
 void intel_dsc_enable(struct intel_encoder *encoder,
 		      struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum pipe pipe = crtc->pipe;
+	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+	u32 dss_ctl1_val = 0;
+	u32 dss_ctl2_val = 0;
 
 	if (!crtc_state->dsc_params.compression_enable)
 		return;
@@ -1017,5 +1023,21 @@  void intel_dsc_enable(struct intel_encoder *encoder,
 
 	intel_dp_send_dsc_pps_sdp(encoder, crtc_state);
 
+	/* Configure DSS_CTL registers for DSC */
+	if (encoder->type == INTEL_OUTPUT_EDP) {
+		dss_ctl1_reg = DSS_CTL1;
+		dss_ctl2_reg = DSS_CTL2;
+	} else {
+		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+	}
+	dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
+	if (crtc_state->dsc_params.dsc_split) {
+		dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
+		dss_ctl1_val |= JOINER_ENABLE;
+	}
+	I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+	I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
 	return;
 }