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Mon, 08 Oct 2018 11:24:44 -0700 (PDT) Received: from rosewood.cam.corp.google.com ([2620:0:1013:11:ad55:b1db:adfe:3b9f]) by smtp.gmail.com with ESMTPSA id g126-v6sm6028452ywf.9.2018.10.08.11.24.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 08 Oct 2018 11:24:44 -0700 (PDT) From: Sean Paul To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/2] drm/msm: a6xx: Fix improper u64 division Date: Mon, 8 Oct 2018 14:24:14 -0400 Message-Id: <20181008182424.108745-2-sean@poorly.run> X-Mailer: git-send-email 2.19.0.605.g01d371f741-goog In-Reply-To: <20181008182424.108745-1-sean@poorly.run> References: <20181008182424.108745-1-sean@poorly.run> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, Sharat Masetty , Sean Paul , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Sean Paul This patch uses the proper do_div() macro to perform u64 division and guards against overflow if the result is too large for the unsigned long return type Fixes: a2c3c0a54d4c drm/msm/a6xx: Add devfreq support for a6xx Cc: Sharat Masetty Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index cdc3d59a659d..631257c297fd 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -761,18 +761,21 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); - u64 busy_cycles; - unsigned long busy_time; + u64 busy_cycles, busy_time; busy_cycles = gmu_read64(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); - busy_time = ((busy_cycles - gpu->devfreq.busy_cycles) * 10) / 192; + busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10; + do_div(busy_time, 192); gpu->devfreq.busy_cycles = busy_cycles; - return busy_time; + if (WARN_ON(busy_time > ~0LU)) + return ~0LU; + + return (unsigned long)busy_time; } static const struct adreno_gpu_funcs funcs = {