| Message ID | 20181010235051.16693-3-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | CRTC background color | expand |
On Wed, Oct 10, 2018 at 04:50:51PM -0700, Matt Roper wrote: > Gen9+ platforms allow CRTC's to be programmed with a background/canvas > color below the programmable planes. Let's expose this for use by > compositors. > > Cc: dri-devel@lists.freedesktop.org > Cc: wei.c.li@intel.com > Cc: harish.krupo.kps@intel.com > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 9 +++++++++ > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > drivers/gpu/drm/i915/intel_display.c | 34 ++++++++++++++++++++++++++++++++++ > 3 files changed, 49 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 4565eda29c87..cc423f7f3e62 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -3254,6 +3254,15 @@ static int i915_display_info(struct seq_file *m, void *unused) > intel_plane_info(m, crtc); > } > > + if (INTEL_GEN(dev_priv) >= 9 && pipe_config->base.active) { > + uint64_t background = pipe_config->base.background_color; > + > + seq_printf(m, "\tbackground color (10bpc): r=%x g=%x b=%x\n", > + DRM_RGBA_RED(background, 10), > + DRM_RGBA_GREEN(background, 10), > + DRM_RGBA_BLUE(background, 10)); > + } > + > seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", > yesno(!crtc->cpu_fifo_underrun_disabled), > yesno(!crtc->pch_fifo_underrun_disabled)); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 20785417953d..988183870f6e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5661,6 +5661,12 @@ enum { > #define PIPEMISC_DITHER_TYPE_SP (0 << 2) > #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) > > +/* Skylake+ pipe bottom (background) color */ > +#define _PIPE_BOTTOM_COLOR_A 0x70034 > +#define PIPE_BOTTOM_GAMMA_ENABLE (1 << 31) > +#define PIPE_BOTTOM_CSC_ENABLE (1 << 30) > +#define PIPE_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _PIPE_BOTTOM_COLOR_A) > + > #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) > #define PIPEB_LINE_COMPARE_INT_EN (1 << 29) > #define PIPEB_HLINE_INT_EN (1 << 28) > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index a145efba9157..2ee402a98e70 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3853,6 +3853,28 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) > clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); > } > > +static void skl_update_background_color(const struct intel_crtc_state *cstate) > +{ > + struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc); > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + uint64_t propval = cstate->base.background_color; > + uint32_t hwval; Just 'val' or 'tmp' would be more consistent with existing code. > + > + /* Hardware is programmed with 10 bits of precision */ > + hwval = DRM_RGBA_RED(propval, 10) << 20 > + | DRM_RGBA_GREEN(propval, 10) << 10 > + | DRM_RGBA_BLUE(propval, 10); > + > + /* > + * Set CSC and gamma for bottom color to ensure background pixels > + * receive the same color transformations as plane content. > + */ > + hwval |= PIPE_BOTTOM_CSC_ENABLE; > + hwval |= PIPE_BOTTOM_GAMMA_ENABLE; Maybe we want these as a separate bugfix up front? > + > + I915_WRITE_FW(PIPE_BOTTOM_COLOR(crtc->pipe), hwval); > +} > + > static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state, > const struct intel_crtc_state *new_crtc_state) > { > @@ -3887,6 +3909,9 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta > else if (old_crtc_state->pch_pfit.enabled) > ironlake_pfit_disable(old_crtc_state); > } > + > + if (new_crtc_state->base.bgcolor_changed) > + skl_update_background_color(new_crtc_state); > } > > static void intel_fdi_normal_train(struct intel_crtc *crtc) > @@ -10791,6 +10816,9 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, > crtc_state->planes_changed = true; > } > > + if (crtc_state->bgcolor_changed) > + pipe_config->update_pipe = true; > + > ret = 0; > if (dev_priv->display.compute_pipe_wm) { > ret = dev_priv->display.compute_pipe_wm(pipe_config); > @@ -13831,6 +13859,7 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc, > > static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) > { > + struct drm_mode_config *mode_config = &dev_priv->drm.mode_config; > struct intel_crtc *intel_crtc; > struct intel_crtc_state *crtc_state = NULL; > struct intel_plane *primary = NULL; > @@ -13905,6 +13934,11 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) > > WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); > > + if (INTEL_GEN(dev_priv) >= 9) > + drm_object_attach_property(&intel_crtc->base.base, > + mode_config->bgcolor_property, > + drm_rgba(16, 0, 0, 0, 0xffff)); > + > return 0; > > fail: > -- > 2.14.4 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 4565eda29c87..cc423f7f3e62 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3254,6 +3254,15 @@ static int i915_display_info(struct seq_file *m, void *unused) intel_plane_info(m, crtc); } + if (INTEL_GEN(dev_priv) >= 9 && pipe_config->base.active) { + uint64_t background = pipe_config->base.background_color; + + seq_printf(m, "\tbackground color (10bpc): r=%x g=%x b=%x\n", + DRM_RGBA_RED(background, 10), + DRM_RGBA_GREEN(background, 10), + DRM_RGBA_BLUE(background, 10)); + } + seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", yesno(!crtc->cpu_fifo_underrun_disabled), yesno(!crtc->pch_fifo_underrun_disabled)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 20785417953d..988183870f6e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5661,6 +5661,12 @@ enum { #define PIPEMISC_DITHER_TYPE_SP (0 << 2) #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) +/* Skylake+ pipe bottom (background) color */ +#define _PIPE_BOTTOM_COLOR_A 0x70034 +#define PIPE_BOTTOM_GAMMA_ENABLE (1 << 31) +#define PIPE_BOTTOM_CSC_ENABLE (1 << 30) +#define PIPE_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _PIPE_BOTTOM_COLOR_A) + #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) #define PIPEB_LINE_COMPARE_INT_EN (1 << 29) #define PIPEB_HLINE_INT_EN (1 << 28) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a145efba9157..2ee402a98e70 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3853,6 +3853,28 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); } +static void skl_update_background_color(const struct intel_crtc_state *cstate) +{ + struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + uint64_t propval = cstate->base.background_color; + uint32_t hwval; + + /* Hardware is programmed with 10 bits of precision */ + hwval = DRM_RGBA_RED(propval, 10) << 20 + | DRM_RGBA_GREEN(propval, 10) << 10 + | DRM_RGBA_BLUE(propval, 10); + + /* + * Set CSC and gamma for bottom color to ensure background pixels + * receive the same color transformations as plane content. + */ + hwval |= PIPE_BOTTOM_CSC_ENABLE; + hwval |= PIPE_BOTTOM_GAMMA_ENABLE; + + I915_WRITE_FW(PIPE_BOTTOM_COLOR(crtc->pipe), hwval); +} + static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -3887,6 +3909,9 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta else if (old_crtc_state->pch_pfit.enabled) ironlake_pfit_disable(old_crtc_state); } + + if (new_crtc_state->base.bgcolor_changed) + skl_update_background_color(new_crtc_state); } static void intel_fdi_normal_train(struct intel_crtc *crtc) @@ -10791,6 +10816,9 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, crtc_state->planes_changed = true; } + if (crtc_state->bgcolor_changed) + pipe_config->update_pipe = true; + ret = 0; if (dev_priv->display.compute_pipe_wm) { ret = dev_priv->display.compute_pipe_wm(pipe_config); @@ -13831,6 +13859,7 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc, static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) { + struct drm_mode_config *mode_config = &dev_priv->drm.mode_config; struct intel_crtc *intel_crtc; struct intel_crtc_state *crtc_state = NULL; struct intel_plane *primary = NULL; @@ -13905,6 +13934,11 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); + if (INTEL_GEN(dev_priv) >= 9) + drm_object_attach_property(&intel_crtc->base.base, + mode_config->bgcolor_property, + drm_rgba(16, 0, 0, 0, 0xffff)); + return 0; fail:
Gen9+ platforms allow CRTC's to be programmed with a background/canvas color below the programmable planes. Let's expose this for use by compositors. Cc: dri-devel@lists.freedesktop.org Cc: wei.c.li@intel.com Cc: harish.krupo.kps@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 9 +++++++++ drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ drivers/gpu/drm/i915/intel_display.c | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+)