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[84.106.84.65]) by smtp.gmail.com with ESMTPSA id b71-v6sm1727008wma.13.2018.10.17.04.09.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 Oct 2018 04:09:49 -0700 (PDT) From: Hans de Goede X-Google-Original-From: Hans de Goede To: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , Daniel Vetter Subject: [PATCH v2 2/2] drm/i915/intel_dsi: Read back pclk set by GOP and use that as pclk v2 Date: Wed, 17 Oct 2018 13:09:43 +0200 Message-Id: <20181017110943.30770-3-hdegoede@redhat.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181017110943.30770-1-hdegoede@redhat.com> References: <20181017110943.30770-1-hdegoede@redhat.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 17 Oct 2018 11:37:00 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hans de Goede , intel-gfx , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP On BYT and CHT the GOP sometimes initializes the pclk at a (slightly) different frequency then the pclk which we've calculated. This commit makes the DSI code read-back the pclk set by the GOP and if that is within a reasonable margin of the calculated pclk, uses that instead. This fixes the first modeset being a full modeset instead of a fast modeset on systems where the GOP pclk is different. Changes in v2: -Use intel_encoder_current_mode() to get the pclk setup by the GOP Signed-off-by: Hans de Goede --- drivers/gpu/drm/i915/intel_dsi_vbt.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c index ac83d6b89ae0..3387b187105c 100644 --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c @@ -506,6 +506,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; + struct drm_display_mode *curr; u32 bpp; u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui; u32 ui_num, ui_den; @@ -583,6 +584,23 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) } else burst_mode_ratio = 100; + /* + * On BYT / CRC the GOP sometimes picks a slightly different pclk, + * read back the GOP configured pclk and prefer it over ours. + */ + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + curr = intel_encoder_current_mode(&intel_dsi->base); + if (curr) { + DRM_DEBUG_KMS("Calculated pclk %d GOP %d\n", + pclk, curr->clock); + if (curr->clock >= (pclk * 9 / 10) && + curr->clock <= (pclk * 11 / 10)) + pclk = curr->clock; + + kfree(curr); + } + } + intel_dsi->burst_mode_ratio = burst_mode_ratio; intel_dsi->pclk = pclk;