| Message ID | 20181102064659.8991-8-manasi.d.navare@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | DSC enabling remaining patches | expand |
On Thu, Nov 01, 2018 at 11:46:47PM -0700, Manasi Navare wrote: > If a eDP panel supports both PSR2 and VDSC, our HW cannot > support both at a time. Give priority to PSR2 if a requested > resolution can be supported without compression else enable > VDSC and keep PSR2 disabled. > > v3: > * Rebase > v2: > * Add warning for DSC and PSR2 enabled together (DK) > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/intel_psr.c | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index bc2d88313ed0..8f063e1e2fb2 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -71,9 +71,9 @@ static bool psr_global_enabled(u32 debug) > static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, > const struct intel_crtc_state *crtc_state) > { > - /* Disable PSR2 by default for all platforms */ > - if (i915_modparams.enable_psr == -1) > - return false; That seems unrelated to DSC? > + /* Cannot enable DSC and PSR2 simultaneously */ > + WARN_ON(crtc_state->dsc_params.compression_enable && > + crtc_state->has_psr2); > > switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { > case I915_PSR_DEBUG_FORCE_PSR1: > @@ -463,6 +463,16 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > if (!dev_priv->psr.sink_psr2_support) > return false; > > + /* > + * DSC and PSR2 cannot be enabled simultaneously. If a requested > + * resolution requires DSC to be enabled, priority is given to DSC > + * over PSR2. > + */ > + if (crtc_state->dsc_params.compression_enable) { > + DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n"); > + return false; > + } > + > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { > psr_max_h = 4096; > psr_max_v = 2304; > -- > 2.18.0
On Fri, Nov 02, 2018 at 07:51:18PM +0200, Ville Syrjälä wrote: > On Thu, Nov 01, 2018 at 11:46:47PM -0700, Manasi Navare wrote: > > If a eDP panel supports both PSR2 and VDSC, our HW cannot > > support both at a time. Give priority to PSR2 if a requested > > resolution can be supported without compression else enable > > VDSC and keep PSR2 disabled. > > > > v3: > > * Rebase > > v2: > > * Add warning for DSC and PSR2 enabled together (DK) > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Cc: Jani Nikula <jani.nikula@intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > --- > > drivers/gpu/drm/i915/intel_psr.c | 16 +++++++++++++--- > > 1 file changed, 13 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > > index bc2d88313ed0..8f063e1e2fb2 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -71,9 +71,9 @@ static bool psr_global_enabled(u32 debug) > > static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, > > const struct intel_crtc_state *crtc_state) > > { > > - /* Disable PSR2 by default for all platforms */ > > - if (i915_modparams.enable_psr == -1) > > - return false; > > That seems unrelated to DSC? Thats a good catch, i think thsi got removed due to a rebase by mistake. I will add it back there. Manasi > > > + /* Cannot enable DSC and PSR2 simultaneously */ > > + WARN_ON(crtc_state->dsc_params.compression_enable && > > + crtc_state->has_psr2); > > > > switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { > > case I915_PSR_DEBUG_FORCE_PSR1: > > @@ -463,6 +463,16 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > > if (!dev_priv->psr.sink_psr2_support) > > return false; > > > > + /* > > + * DSC and PSR2 cannot be enabled simultaneously. If a requested > > + * resolution requires DSC to be enabled, priority is given to DSC > > + * over PSR2. > > + */ > > + if (crtc_state->dsc_params.compression_enable) { > > + DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n"); > > + return false; > > + } > > + > > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { > > psr_max_h = 4096; > > psr_max_v = 2304; > > -- > > 2.18.0 > > -- > Ville Syrjälä > Intel > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index bc2d88313ed0..8f063e1e2fb2 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -71,9 +71,9 @@ static bool psr_global_enabled(u32 debug) static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, const struct intel_crtc_state *crtc_state) { - /* Disable PSR2 by default for all platforms */ - if (i915_modparams.enable_psr == -1) - return false; + /* Cannot enable DSC and PSR2 simultaneously */ + WARN_ON(crtc_state->dsc_params.compression_enable && + crtc_state->has_psr2); switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { case I915_PSR_DEBUG_FORCE_PSR1: @@ -463,6 +463,16 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, if (!dev_priv->psr.sink_psr2_support) return false; + /* + * DSC and PSR2 cannot be enabled simultaneously. If a requested + * resolution requires DSC to be enabled, priority is given to DSC + * over PSR2. + */ + if (crtc_state->dsc_params.compression_enable) { + DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n"); + return false; + } + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { psr_max_h = 4096; psr_max_v = 2304;