From patchwork Sun Nov 25 14:40:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Pinchart X-Patchwork-Id: 10697553 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DCFDE14E2 for ; Mon, 26 Nov 2018 04:12:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CD19C2986C for ; Mon, 26 Nov 2018 04:12:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C1BB729879; Mon, 26 Nov 2018 04:12:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6F33D2986C for ; Mon, 26 Nov 2018 04:12:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A3B9989BFC; Mon, 26 Nov 2018 04:11:48 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by gabe.freedesktop.org (Postfix) with ESMTPS id 79BC089BF8 for ; Sun, 25 Nov 2018 14:40:17 +0000 (UTC) Received: from avalon.bb.dnainternet.fi (dfj612ybrt5fhg77mgycy-3.rev.dnainternet.fi [IPv6:2001:14ba:21f5:5b00:2e86:4862:ef6a:2804]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id EA3ADE7C; Sun, 25 Nov 2018 15:40:12 +0100 (CET) From: Laurent Pinchart To: dri-devel@lists.freedesktop.org Subject: [PATCH 3/5] drm: rcar-du: Disable unused DPAD outputs Date: Sun, 25 Nov 2018 16:40:29 +0200 Message-Id: <20181125144031.4407-4-laurent.pinchart+renesas@ideasonboard.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181125144031.4407-1-laurent.pinchart+renesas@ideasonboard.com> References: <20181125144031.4407-1-laurent.pinchart+renesas@ideasonboard.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-renesas-soc@vger.kernel.org, kieran.bingham@ideasonboard.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP DU channels are routed to DPAD outputs in an SoC-dependent way. The routing can be fixed (e.g. DU3 to DPAD0 on H3) or configurable (e.g. DU0 or DU1 to DPAD0 on D3/E3). The hardware offers no option to disconnect DPAD outputs, which are thus always driven by a DU channel. On SoCs that have less DU channels than DU outputs, such as D3 and E3, the DPAD output is always driven when all channels are in used by other outputs (such as the internal LVDS and HDMI encoders). This creates an unwanted clone on the DPAD output. However, the parallel output of the DU channels routed to DPAD can be set to fixed levels in the DU channels themselves through the DOFLR group register. Use this to turn the DPAD on or off by driving fixed signals at the output of any DU channel not routed to a DPAD output. This doesn't affect the DU output signals going to other outputs. Signed-off-by: Laurent Pinchart Reviewed-by: Kieran Bingham --- drivers/gpu/drm/rcar-du/rcar_du_group.c | 42 +++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index 7e440f61977f..5aaf41b7a2ca 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -287,6 +287,46 @@ int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu) return 0; } +static void rcar_du_group_set_output_levels(struct rcar_du_group *rgrp) +{ + static const u32 doflr_values[2] = { + DOFLR_HSYCFL0 | DOFLR_VSYCFL0 | DOFLR_ODDFL0 | + DOFLR_DISPFL0 | DOFLR_CDEFL0 | DOFLR_RGBFL0, + DOFLR_HSYCFL1 | DOFLR_VSYCFL1 | DOFLR_ODDFL1 | + DOFLR_DISPFL1 | DOFLR_CDEFL1 | DOFLR_RGBFL1, + }; + static const u32 dpad_mask = BIT(RCAR_DU_OUTPUT_DPAD1) + | BIT(RCAR_DU_OUTPUT_DPAD0); + struct rcar_du_device *rcdu = rgrp->dev; + u32 doflr = DOFLR_CODE; + unsigned int i; + + if (rcdu->info->gen < 2) + return; + + /* + * The DPAD outputs can't be controlled directly. However, the parallel + * output of the DU channels routed to DPAD can be set to fixed levels + * through the DOFLR group register. Use this to turn the DPAD on or off + * by driving fixed signals at the output of any DU channel not routed + * to a DPAD output. This doesn't affect the DU output signals going to + * other outputs, such as the internal LVDS and HDMI encoders. + */ + + for (i = 0; i < rgrp->num_crtcs; ++i) { + struct rcar_du_crtc_state *rstate; + struct rcar_du_crtc *rcrtc; + + rcrtc = &rcdu->crtcs[rgrp->index * 2 + i]; + rstate = to_rcar_crtc_state(rcrtc->crtc.state); + + if (!(rstate->outputs & dpad_mask)) + doflr |= doflr_values[i]; + } + + rcar_du_group_write(rgrp, DOFLR, doflr); +} + int rcar_du_group_set_routing(struct rcar_du_group *rgrp) { struct rcar_du_device *rcdu = rgrp->dev; @@ -306,5 +346,7 @@ int rcar_du_group_set_routing(struct rcar_du_group *rgrp) rcar_du_group_write(rgrp, DORCR, dorcr); + rcar_du_group_set_output_levels(rgrp); + return rcar_du_set_dpad0_vsp1_routing(rgrp->dev); }