| Message ID | 20181204151702.8514-5-jonathan@marek.ca (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v4,1/5] drm/msm/mdp4: add lcdc-align-lsb flag to control lane alignment | expand |
On Tue, 4 Dec 2018 10:17:01 -0500, Jonathan Marek wrote: > Document the new amd,imageon compatible, used for non-qcom hardware that > uses the drm/msm driver (iMX5). > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > --- > Documentation/devicetree/bindings/display/msm/gpu.txt | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 43fac0fe0..ac8df3b87 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -1,11 +1,13 @@ Qualcomm adreno/snapdragon GPU Required properties: -- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" +- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or + "amd,imageon-XYZ.W", "amd,imageon" for example: "qcom,adreno-306.0", "qcom,adreno" Note that you need to list the less specific "qcom,adreno" (since this is what the device is matched on), in addition to the more specific with the chip-id. + If "amd,imageon" is used, there should be no top level msm device. - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt signal from the gpu. - clocks: device clocks
Document the new amd,imageon compatible, used for non-qcom hardware that uses the drm/msm driver (iMX5). Signed-off-by: Jonathan Marek <jonathan@marek.ca> --- Documentation/devicetree/bindings/display/msm/gpu.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)