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Thu, 6 Dec 2018 08:18:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 63BA26E533; Thu, 6 Dec 2018 08:17:54 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from EUR02-HE1-obe.outbound.protection.outlook.com (mail-eopbgr10082.outbound.protection.outlook.com [40.107.1.82]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4C98A6E3CA for ; Wed, 5 Dec 2018 10:19:01 +0000 (UTC) Received: from AM3PR08MB0611.eurprd08.prod.outlook.com (10.163.188.149) by AM3PR08MB0644.eurprd08.prod.outlook.com (10.163.188.158) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1404.19; Wed, 5 Dec 2018 10:18:57 +0000 Received: from AM3PR08MB0611.eurprd08.prod.outlook.com ([fe80::38d5:d5ee:b90c:901c]) by AM3PR08MB0611.eurprd08.prod.outlook.com ([fe80::38d5:d5ee:b90c:901c%4]) with mapi id 15.20.1382.023; Wed, 5 Dec 2018 10:18:57 +0000 From: "james qian wang (Arm Technology China)" To: Liviu Dudau Subject: [PATCH v1 2/9] dt/bindings: drm/komeda: Add DT bindings for ARM display processor D71 Thread-Topic: [PATCH v1 2/9] dt/bindings: drm/komeda: Add DT bindings for ARM display processor D71 Thread-Index: AQHUjIPu5G0ecZ3ps0mHJA0fC+KmUQ== Date: Wed, 5 Dec 2018 10:18:57 +0000 Message-ID: <20181205101635.7696-3-james.qian.wang@arm.com> References: <20181205101635.7696-1-james.qian.wang@arm.com> In-Reply-To: <20181205101635.7696-1-james.qian.wang@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [113.29.88.7] x-clientproxiedby: SYCPR01CA0014.ausprd01.prod.outlook.com (2603:10c6:10:31::26) To AM3PR08MB0611.eurprd08.prod.outlook.com (2a01:111:e400:c408::21) x-ms-exchange-messagesentrepresentingtype: 1 x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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Signed-off-by: James (Qian) Wang --- .../bindings/display/arm/arm,komeda.txt | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/arm/arm,komeda.txt diff --git a/Documentation/devicetree/bindings/display/arm/arm,komeda.txt b/Documentation/devicetree/bindings/display/arm/arm,komeda.txt new file mode 100644 index 000000000000..d4b53c11b2a2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/arm/arm,komeda.txt @@ -0,0 +1,87 @@ +Device Tree bindings for ARM Komeda display driver + +Required properties: +- compatible: Should be "arm,mali-d71" +- reg: Physical base address and length of the registers in the system +- interrupts: the interrupt line numbers of the device in the system +- interrupt-names: contains the names of the IRQs in the order they were + provided in the "interrupts" property. Must contain: "DPU". +- clocks: A list of phandle + clock-specifier pairs, one for each entry + in 'clock-names' +- clock-names: A list of clock names. It should contain: + - "pclk": for the APB interface clock + - "mclk": for the main processor clock +- #address-cells: Must be 1 +- #size-cells: Must be 0 + +Required properties for sub-node: pipeline@nq +Each device contains one or two pipeline sub-nodes (at least one), each +pipeline node should provide properties: +- reg: Zero-indexed identifier for the pipeline +- clocks: A list of phandle + clock-specifier pairs, one for each entry + in 'clock-names' +- clock-names: should contain: + - "aclk": AXI interface clock + - "pxclk": pixel clock + +- port: each pipeline connect to an encoder input port. The connection is + modelled using the OF graph bindings specified in + Documentation/devicetree/bindings/graph.txt + +Optional properties: + - memory-region: phandle to a node describing memory (see + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) + to be used for the framebuffer; if not present, the framebuffer may + be located anywhere in memory. + +Example: +/ { + ... + + dp0: display@c00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,mali-d71"; + reg = <0xc00000 0x20000>; + interrupts = <0 168 4>; + interrupt-names = "DPU"; + clocks = <&dpu_mclk>, <&dpu_aclk>; + clock-names = "mclk", "pclk"; + + pl0: pipeline@0 { + clocks = <&fpgaosc2>, <&dpu_aclk>; + clock-names = "pxclk", "aclk"; + reg = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_pl0_out: endpoint { + remote-endpoint = <&db_dvi0_in>; + }; + }; + }; + }; + pl1: pipeline@1 { + clocks = <&fpgaosc2>, <&dpu_aclk>; + clock-names = "pxclk", "aclk"; + reg = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_pl1_out: endpoint { + remote-endpoint = <&db_dvi1_in>; + }; + }; + }; + }; + }; + ... +};