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DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR08MB0262; H:AM3PR08MB0611.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: /aAYzVk5ng2c7eHZsQrFeZ35a6Uk+O8mGw0gqdDv+lt4/lBPYnG2zReJbcZxLlGpcaPSdysip37Ehb985j4BZjDdIR7TLtIHjNNU++YEC6ZPlSmha2Hb/2w4QldnWeJTGEd82B064qP1lDfFLsLrifIJUcxEsSft/ntkcLyQI/HZByN9GfLpM7wtLQydL0jbfhVKPNZXpai/gHwmWHBkuZP3QC9iwpOZdnEgxoUCwU+yqt4XeJqFtK/FTcCg8nq0ipwf8YX8Ugm5xsUyDX1vYlKj5eZFfcAa4XtVfKdgHrTmvz0ac+jX00DjabXdiSx3 spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 94df6142-c1d6-4c62-17d1-08d66981c941 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Dec 2018 09:25:47.1460 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0262 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd , Ayan Halder , "Tiannan Zhu \(Arm Technology China\)" , "airlied@linux.ie" , "Jonathan Chai \(Arm Technology China\)" , Alexandru-Cosmin Gheorghe , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "Julien Yin \(Arm Technology China\)" , "yamada.masahiro@socionext.com" , "james qian wang \(Arm Technology China\)" , "malidp@foss.arm.com" , "Yiqi Kang \(Arm Technology China\)" , "maxime.ripard@bootlin.com" , "thomas Sun \(Arm Technology China\)" , "Jin Gao \(Arm Technology China\)" , "Lowry Li \(Arm Technology China\)" , "sean@poorly.run" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP A komeda flush is comprised two steps: 1. update pipeline/component state to HW. 2. call dev_func->flush to notify HW to kickoff the update. Signed-off-by: James (Qian) Wang --- .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 11 ++++++ .../gpu/drm/arm/display/komeda/komeda_crtc.c | 33 +++++++++++++++++ .../gpu/drm/arm/display/komeda/komeda_dev.h | 3 ++ .../drm/arm/display/komeda/komeda_pipeline.h | 5 +++ .../display/komeda/komeda_pipeline_state.c | 37 +++++++++++++++++++ 5 files changed, 89 insertions(+) diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c index 895603695d79..ecbcf26e8ad6 100644 --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c @@ -241,6 +241,16 @@ static int d71_disable_irq(struct komeda_dev *mdev) return 0; } +static void d71_flush(struct komeda_dev *mdev, + int master_pipe, u32 active_pipes) +{ + struct d71_dev *d71 = mdev->chip_data; + u32 reg_offset = (master_pipe == 0) ? + GCU_CONFIG_VALID0 : GCU_CONFIG_VALID1; + + malidp_write32(d71->gcu_addr, reg_offset, GCU_CONFIG_CVAL); +} + static int d71_reset(struct d71_dev *d71) { u32 __iomem *gcu = d71->gcu_addr; @@ -451,6 +461,7 @@ static struct komeda_dev_funcs d71_chip_funcs = { .irq_handler = d71_irq_handler, .enable_irq = d71_enable_irq, .disable_irq = d71_disable_irq, + .flush = d71_flush, }; struct komeda_dev_funcs * diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c index f84024aae155..b4640971e47e 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -58,8 +58,41 @@ void komeda_crtc_handle_event(struct komeda_crtc *kcrtc, DRM_INFO("FLIP Done.\n"); } +static void +komeda_crtc_do_flush(struct drm_crtc *crtc, + struct drm_crtc_state *old) +{ + struct komeda_crtc *kcrtc = to_kcrtc(crtc); + struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(crtc->state); + struct komeda_dev *mdev = kcrtc->base.dev->dev_private; + struct komeda_pipeline *master = kcrtc->master; + + DRM_DEBUG_ATOMIC("CRTC%d_FLUSH: active_pipes: 0x%x, affected: 0x%x.\n", + drm_crtc_index(crtc), + kcrtc_st->active_pipes, kcrtc_st->affected_pipes); + + /* step 1: update the pipeline/component state to HW */ + if (has_bit(master->id, kcrtc_st->affected_pipes)) + komeda_pipeline_update(master, old->state); + + /* step 2: notify the HW to kickoff the update */ + mdev->funcs->flush(mdev, master->id, kcrtc_st->active_pipes); +} + +static void +komeda_crtc_atomic_flush(struct drm_crtc *crtc, + struct drm_crtc_state *old) +{ + /* commit with modeset will be handled in enable/disable */ + if (drm_atomic_crtc_needs_modeset(crtc->state)) + return; + + komeda_crtc_do_flush(crtc, old); +} + struct drm_crtc_helper_funcs komeda_crtc_helper_funcs = { .atomic_check = komeda_crtc_atomic_check, + .atomic_flush = komeda_crtc_atomic_flush, }; static const struct drm_crtc_funcs komeda_crtc_funcs = { diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h index 5f96d2f57c4e..686ce97ce30f 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h @@ -106,6 +106,9 @@ struct komeda_dev_funcs { /** @dump_register: Optional, dump registers to seq_file */ void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq); + /** @flush: Notify the HW to flush or kickoff the update */ + void (*flush)(struct komeda_dev *mdev, + int master_pipe, u32 active_pipes); }; /** diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h index 9a17d0152021..9a96ee906a36 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h @@ -421,4 +421,9 @@ int komeda_build_display_data_flow(struct komeda_crtc *kcrtc, int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe, struct komeda_crtc_state *kcrtc_st); +void komeda_pipeline_disable(struct komeda_pipeline *pipe, + struct drm_atomic_state *old_state); +void komeda_pipeline_update(struct komeda_pipeline *pipe, + struct drm_atomic_state *old_state); + #endif /* _KOMEDA_PIPELINE_H_*/ diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c index 920d2b40e9cc..19d8ed904bf7 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c @@ -42,6 +42,18 @@ komeda_pipeline_get_state(struct komeda_pipeline *pipe, return priv_to_pipe_st(priv_st); } +struct komeda_pipeline_state * +komeda_pipeline_get_old_state(struct komeda_pipeline *pipe, + struct drm_atomic_state *state) +{ + struct drm_private_state *priv_st; + + priv_st = drm_atomic_get_old_private_obj_state(state, &pipe->obj); + if (priv_st) + return priv_to_pipe_st(priv_st); + return NULL; +} + struct komeda_pipeline_state * komeda_pipeline_get_new_state(struct komeda_pipeline *pipe, struct drm_atomic_state *state) @@ -536,3 +548,28 @@ int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe, return 0; } + +void komeda_pipeline_update(struct komeda_pipeline *pipe, + struct drm_atomic_state *old_state) +{ + struct komeda_pipeline_state *new = priv_to_pipe_st(pipe->obj.state); + struct komeda_pipeline_state *old; + struct komeda_component *c; + u32 id, changed_comps = 0; + + old = komeda_pipeline_get_old_state(pipe, old_state); + + changed_comps = new->active_comps | old->active_comps; + + DRM_DEBUG_ATOMIC("PIPE%d: active_comps: 0x%x, changed: 0x%x.\n", + pipe->id, new->active_comps, changed_comps); + + dp_for_each_set_bit(id, changed_comps) { + c = komeda_pipeline_get_component(pipe, id); + + if (new->active_comps & BIT(c->id)) + c->funcs->update(c, priv_to_comp_st(c->obj.state)); + else + c->funcs->disable(c); + } +}