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Mon, 24 Dec 2018 09:26:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5193A6E555; Mon, 24 Dec 2018 09:26:13 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from EUR03-AM5-obe.outbound.protection.outlook.com (mail-eopbgr30083.outbound.protection.outlook.com [40.107.3.83]) by gabe.freedesktop.org (Postfix) with ESMTPS id E2AA56E555 for ; Mon, 24 Dec 2018 09:26:11 +0000 (UTC) Received: from AM3PR08MB0611.eurprd08.prod.outlook.com (10.163.188.149) by AM3PR08MB0262.eurprd08.prod.outlook.com (10.161.35.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1446.23; Mon, 24 Dec 2018 09:26:09 +0000 Received: from AM3PR08MB0611.eurprd08.prod.outlook.com ([fe80::3c73:534c:9c6e:352d]) by AM3PR08MB0611.eurprd08.prod.outlook.com ([fe80::3c73:534c:9c6e:352d%2]) with mapi id 15.20.1446.026; Mon, 24 Dec 2018 09:26:09 +0000 From: "james qian wang (Arm Technology China)" To: Liviu Dudau Subject: [PATCH 05/11] drm/komeda: Add komeda_crtc_prepare/unprepare Thread-Topic: [PATCH 05/11] drm/komeda: Add komeda_crtc_prepare/unprepare Thread-Index: AQHUm2q067w9tQBgxkG49VShivGxWA== Date: Mon, 24 Dec 2018 09:26:09 +0000 Message-ID: <20181224092435.2792-6-james.qian.wang@arm.com> References: <20181224092435.2792-1-james.qian.wang@arm.com> In-Reply-To: <20181224092435.2792-1-james.qian.wang@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [113.29.88.7] x-clientproxiedby: SYXPR01CA0099.ausprd01.prod.outlook.com (2603:10c6:0:2e::32) To AM3PR08MB0611.eurprd08.prod.outlook.com (2a01:111:e400:c408::21) x-ms-exchange-messagesentrepresentingtype: 1 x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR08MB0262; H:AM3PR08MB0611.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: yreR2hCBHkDp2Xpre+dooURGyem2uRcoJWeYcQmoF3iT4ZpHHyGeQQzHVNpC/D9nTDpbvuaHuTy3pjEjsfqJyCMCvcxu+pdfnB+5fXeZaUxPVI0cAExpoXdkd9VW2QueEfRmvyQBTmDTwfe0mh4cyOgVyxKELpioaDOX0O86l1NOLTKzlF+I8NqtV77iqrs5kaW9/M9Vh/NVRqZeUzn4R7nPdsNtp5mmcVd3QPcALMEUVhPBJC+GNJyFf4X7umGJrfBt6EucmNrpwtx2sZYPXdRDgxKeomphfQfYPGMwwO3VKutimJwBwnWdx0sOks3J spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: b53ef5d6-af61-4955-2d5b-08d66981d672 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Dec 2018 09:26:09.2811 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0262 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd , Ayan Halder , "Tiannan Zhu \(Arm Technology China\)" , "airlied@linux.ie" , "Jonathan Chai \(Arm Technology China\)" , Alexandru-Cosmin Gheorghe , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "Julien Yin \(Arm Technology China\)" , "yamada.masahiro@socionext.com" , "james qian wang \(Arm Technology China\)" , "malidp@foss.arm.com" , "Yiqi Kang \(Arm Technology China\)" , "maxime.ripard@bootlin.com" , "thomas Sun \(Arm Technology China\)" , "Jin Gao \(Arm Technology China\)" , "Lowry Li \(Arm Technology China\)" , "sean@poorly.run" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP These two function will be used by komeda_crtc_enable/disable to do some prepartion works when enable/disable a crtc. like enable a crtc: 1. Adjust display operation mode. 2. Enable/prepare needed clk. Signed-off-by: James (Qian) Wang --- .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 32 ++++++ .../gpu/drm/arm/display/komeda/komeda_crtc.c | 104 ++++++++++++++++++ .../gpu/drm/arm/display/komeda/komeda_dev.c | 2 + .../gpu/drm/arm/display/komeda/komeda_dev.h | 27 +++++ 4 files changed, 165 insertions(+) diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c index ecbcf26e8ad6..39b3c84cf483 100644 --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c @@ -241,6 +241,37 @@ static int d71_disable_irq(struct komeda_dev *mdev) return 0; } +static int to_d71_opmode(int core_mode) +{ + switch (core_mode) { + case KOMEDA_MODE_DISP0: + return DO0_ACTIVE_MODE; + case KOMEDA_MODE_DISP1: + return DO1_ACTIVE_MODE; + case KOMEDA_MODE_DUAL_DISP: + return DO01_ACTIVE_MODE; + case KOMEDA_MODE_INACTIVE: + return INACTIVE_MODE; + default: + WARN(1, "Unknown operation mode"); + return INACTIVE_MODE; + } +} + +static int d71_change_opmode(struct komeda_dev *mdev, int new_mode) +{ + struct d71_dev *d71 = mdev->chip_data; + u32 opmode = to_d71_opmode(new_mode); + int ret; + + malidp_write32_mask(d71->gcu_addr, BLK_CONTROL, 0x7, opmode); + + ret = dp_wait_cond(((malidp_read32(d71->gcu_addr, BLK_CONTROL) & 0x7) == opmode), + 100, 1000, 10000); + + return ret > 0 ? 0 : -ETIMEDOUT; +} + static void d71_flush(struct komeda_dev *mdev, int master_pipe, u32 active_pipes) { @@ -461,6 +492,7 @@ static struct komeda_dev_funcs d71_chip_funcs = { .irq_handler = d71_irq_handler, .enable_irq = d71_enable_irq, .disable_irq = d71_disable_irq, + .change_opmode = d71_change_opmode, .flush = d71_flush, }; diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c index 05bdff137e50..9c176ea59303 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -40,6 +40,110 @@ komeda_crtc_atomic_check(struct drm_crtc *crtc, return 0; } +u32 komeda_calc_mclk(struct komeda_crtc_state *kcrtc_st) +{ + unsigned long mclk = kcrtc_st->base.adjusted_mode.clock * 1000; + + return mclk; +} + +/* For active a crtc, mainly need two parts of preparation + * 1. adjust display operation mode. + * 2. enable needed clk + */ +static int +komeda_crtc_prepare(struct komeda_crtc *kcrtc) +{ + struct komeda_dev *mdev = kcrtc->base.dev->dev_private; + struct komeda_pipeline *master = kcrtc->master; + struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(kcrtc->base.state); + unsigned long pxlclk_rate = kcrtc_st->base.adjusted_mode.clock * 1000; + u32 new_mode; + int err; + + mutex_lock(&mdev->lock); + + new_mode = mdev->dpmode | BIT(master->id); + if (WARN_ON(new_mode == mdev->dpmode)) { + err = 0; + goto unlock; + } + + err = mdev->funcs->change_opmode(mdev, new_mode); + if (err) { + DRM_ERROR("failed to change opmode: 0x%x -> 0x%x.\n,", + mdev->dpmode, new_mode); + goto unlock; + } + + mdev->dpmode = new_mode; + /* Only need to enable mclk on single display mode, but no need to + * enable mclk it on dual display mode, since the dual mode always + * switch from single display mode, the mclk already enabled, no need + * to enable it again. + */ + if (new_mode != KOMEDA_MODE_DUAL_DISP) { + err = clk_set_rate(mdev->mclk, komeda_calc_mclk(kcrtc_st)); + if (err) + DRM_ERROR("failed to set mclk.\n"); + err = clk_prepare_enable(mdev->mclk); + if (err) + DRM_ERROR("failed to enable mclk.\n"); + } + + err = clk_prepare_enable(master->aclk); + if (err) + DRM_ERROR("failed to enable axi clk for pipe%d.\n", master->id); + err = clk_set_rate(master->pxlclk, pxlclk_rate); + if (err) + DRM_ERROR("failed to set pxlclk for pipe%d\n", master->id); + err = clk_prepare_enable(master->pxlclk); + if (err) + DRM_ERROR("failed to enable pxl clk for pipe%d.\n", master->id); + +unlock: + mutex_unlock(&mdev->lock); + + return err; +} + +static int +komeda_crtc_unprepare(struct komeda_crtc *kcrtc) +{ + struct komeda_dev *mdev = kcrtc->base.dev->dev_private; + struct komeda_pipeline *master = kcrtc->master; + u32 new_mode; + int err; + + mutex_lock(&mdev->lock); + + new_mode = mdev->dpmode & (~BIT(master->id)); + + if (WARN_ON(new_mode == mdev->dpmode)) { + err = 0; + goto unlock; + } + + err = mdev->funcs->change_opmode(mdev, new_mode); + if (err) { + DRM_ERROR("failed to change opmode: 0x%x -> 0x%x.\n,", + mdev->dpmode, new_mode); + goto unlock; + } + + mdev->dpmode = new_mode; + + clk_disable_unprepare(master->pxlclk); + clk_disable_unprepare(master->aclk); + if (new_mode == KOMEDA_MODE_INACTIVE) + clk_disable_unprepare(mdev->mclk); + +unlock: + mutex_unlock(&mdev->lock); + + return err; +} + void komeda_crtc_handle_event(struct komeda_crtc *kcrtc, struct komeda_events *evts) { diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.c b/drivers/gpu/drm/arm/display/komeda/komeda_dev.c index cf3c8d5f5d90..811f3617e893 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.c @@ -148,6 +148,8 @@ struct komeda_dev *komeda_dev_create(struct device *dev) if (!mdev) return ERR_PTR(-ENOMEM); + mutex_init(&mdev->lock); + mdev->dev = dev; mdev->reg_base = devm_ioremap_resource(dev, io_res); if (IS_ERR(mdev->reg_base)) { diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h index 686ce97ce30f..18dd82b09340 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h @@ -106,11 +106,34 @@ struct komeda_dev_funcs { /** @dump_register: Optional, dump registers to seq_file */ void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq); + /** + * @change_opmode: + * + * Notify HW to switch to a new display operation mode. + */ + int (*change_opmode)(struct komeda_dev *mdev, int new_mode); /** @flush: Notify the HW to flush or kickoff the update */ void (*flush)(struct komeda_dev *mdev, int master_pipe, u32 active_pipes); }; +/** + * DISPLAY_MODE describes how many display been enabled, and which will be + * passed to CHIP by &komeda_dev_funcs->change_opmode(), then CHIP can do the + * pipeline resources assignment according to this usage hint. + * - KOMEDA_MODE_DISP0: Only one display enabled, pipeline-0 work as master. + * - KOMEDA_MODE_DISP1: Only one display enabled, pipeline-0 work as master. + * - KOMEDA_MODE_DUAL_DISP: Dual display mode, both display has been enabled. + * And D71 supports assign two pipelines to one single display on mode + * KOMEDA_MODE_DISP0/DISP1 + */ +enum { + KOMEDA_MODE_INACTIVE = 0, + KOMEDA_MODE_DISP0 = BIT(0), + KOMEDA_MODE_DISP1 = BIT(1), + KOMEDA_MODE_DUAL_DISP = KOMEDA_MODE_DISP0 | KOMEDA_MODE_DISP1, +}; + /** * struct komeda_dev * @@ -133,6 +156,10 @@ struct komeda_dev { /** @irq: irq number */ u32 irq; + /* TODO: manage the dpmode by a drm_private_obj */ + struct mutex lock; /* use to protect dpmode */ + u32 dpmode; /* current display mode */ + int n_pipelines; struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES];