From patchwork Thu Jan 24 18:02:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 10779801 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9247A13BF for ; Thu, 24 Jan 2019 18:03:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 86B95326D0 for ; Thu, 24 Jan 2019 18:03:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8441C32827; Thu, 24 Jan 2019 18:03:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 180C9326D0 for ; Thu, 24 Jan 2019 18:03:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 592F86F207; Thu, 24 Jan 2019 18:03:20 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by gabe.freedesktop.org (Postfix) with ESMTPS id 44D0E6F204 for ; Thu, 24 Jan 2019 18:03:15 +0000 (UTC) Received: by mail-wr1-x442.google.com with SMTP id t27so7499899wra.6 for ; Thu, 24 Jan 2019 10:03:15 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cUH3hZoO0g/LZ+pZUMo8PX/7722b7rvBvBxyOPDoCcc=; b=EuXb34mGf68j/MIIAZ4+DqbMPrfmxQD8209aY0Zx9IDYJMqJnCe9BEcYCLieTXLUqM LCihXnuAdyceRaeXdhyDJzeWnoEnK8i+K2Ferx6l83jhzHgp8GEei/xhxB2nAl5j1Pt+ EUcglmmDKmA3biIunXlaKDKxqYChMVxERIAvdEqo3VDs3NacnhNA5SObc1p/EK0vJdiy O0TXAE9mPp7jMbRUjuCra8+vO7e/Lw60DE2oPRsS3/JPztOBjqEkLV6iOWnn7dQ7Ve3k 72e+LSIU6jxw+V8D7PioNrU14CzpPp3BpB0lsrzjW0DB60/F7afJpiRSzlZMJ74e/FJD mVzw== X-Gm-Message-State: AJcUukeQc9kfZkQBq7Q8hAYl3aEW9uBgj+niIxkPCrdJssuht2sa+smO d4vEsb2l7LoD4XCiGL+e/lo= X-Google-Smtp-Source: ALg8bN7P84H53gREw3NL8ptamWkAYt1H3TEpEXlp+zy7vKaXD6tkMljBuqsQJEO9AmGhqIR8vL/LGQ== X-Received: by 2002:adf:82f1:: with SMTP id 104mr8526751wrc.131.1548352993231; Thu, 24 Jan 2019 10:03:13 -0800 (PST) Received: from localhost (pD9E51040.dip0.t-ipconnect.de. [217.229.16.64]) by smtp.gmail.com with ESMTPSA id l21sm7809934wmh.29.2019.01.24.10.03.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 24 Jan 2019 10:03:12 -0800 (PST) From: Thierry Reding To: Thierry Reding Subject: [PATCH v2 10/13] drm/tegra: Restrict IOVA space to DMA mask Date: Thu, 24 Jan 2019 19:02:51 +0100 Message-Id: <20190124180254.20080-11-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190124180254.20080-1-thierry.reding@gmail.com> References: <20190124180254.20080-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, Dmitry Osipenko , dri-devel@lists.freedesktop.org, Mikko Perttunen Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding On Tegra186 and later, the ARM SMMU provides an input address space that is 48 bits wide. However, memory clients can only address up to 40 bits. If the geometry is used as-is, allocations of IOVA space can end up in a region that cannot be addressed by the memory clients. To fix this, restrict the IOVA space to the DMA mask of the host1x device. Note that, technically, the IOVA space needs to be restricted to the intersection of the DMA masks for all clients that are attached to the IOMMU domain. In practice using the DMA mask of the host1x device is sufficient because all host1x clients share the same DMA mask. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/drm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 271c7a5fc954..0c5f1e6a0446 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -136,11 +136,12 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags) if (tegra->domain) { u64 carveout_start, carveout_end, gem_start, gem_end; + u64 dma_mask = dma_get_mask(&device->dev); dma_addr_t start, end; unsigned long order; - start = tegra->domain->geometry.aperture_start; - end = tegra->domain->geometry.aperture_end; + start = tegra->domain->geometry.aperture_start & dma_mask; + end = tegra->domain->geometry.aperture_end & dma_mask; gem_start = start; gem_end = end - CARVEOUT_SZ;