From patchwork Wed Feb 13 14:45:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Francis, David" X-Patchwork-Id: 10810077 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 245796C2 for ; Wed, 13 Feb 2019 14:45:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 10E2028733 for ; Wed, 13 Feb 2019 14:45:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 04FFA29970; Wed, 13 Feb 2019 14:45:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8C49028733 for ; Wed, 13 Feb 2019 14:45:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D25A589FDB; Wed, 13 Feb 2019 14:45:49 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from NAM01-BN3-obe.outbound.protection.outlook.com (mail-eopbgr740058.outbound.protection.outlook.com [40.107.74.58]) by gabe.freedesktop.org (Postfix) with ESMTPS id D8F0B89FA6; Wed, 13 Feb 2019 14:45:47 +0000 (UTC) Received: from BN4PR12CA0004.namprd12.prod.outlook.com (2603:10b6:403:2::14) by MN2PR12MB2974.namprd12.prod.outlook.com (2603:10b6:208:c2::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1622.16; Wed, 13 Feb 2019 14:45:46 +0000 Received: from CO1NAM03FT057.eop-NAM03.prod.protection.outlook.com (2a01:111:f400:7e48::203) by BN4PR12CA0004.outlook.office365.com (2603:10b6:403:2::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1622.16 via Frontend Transport; Wed, 13 Feb 2019 14:45:45 +0000 Received-SPF: SoftFail (protection.outlook.com: domain of transitioning amd.com discourages use of 165.204.84.17 as permitted sender) Received: from SATLEXCHOV01.amd.com (165.204.84.17) by CO1NAM03FT057.mail.protection.outlook.com (10.152.81.124) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.1580.10 via Frontend Transport; Wed, 13 Feb 2019 14:45:45 +0000 Received: from localhost.localdomain (10.180.168.240) by SATLEXCHOV01.amd.com (10.181.40.71) with Microsoft SMTP Server id 14.3.389.1; Wed, 13 Feb 2019 08:45:41 -0600 From: David Francis To: Subject: [PATCH 2/3] drm/dsc: Add native 420 and 422 support to compute_rc_params Date: Wed, 13 Feb 2019 09:45:35 -0500 Message-ID: <20190213144536.21661-3-David.Francis@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190213144536.21661-1-David.Francis@amd.com> References: <20190213144536.21661-1-David.Francis@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:165.204.84.17; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(346002)(396003)(376002)(136003)(39860400002)(2980300002)(189003)(199004)(47776003)(72206003)(53936002)(51416003)(76176011)(49486002)(126002)(1076003)(476003)(2616005)(486006)(6666004)(356004)(104016004)(2906002)(81166006)(186003)(11346002)(426003)(105596002)(446003)(50226002)(336012)(8936002)(2351001)(316002)(97736004)(54906003)(68736007)(16586007)(478600001)(4326008)(36756003)(50466002)(305945005)(48376002)(6916009)(8676002)(26005)(77096007)(81156014)(106466001)(86362001); DIR:OUT; SFP:1101; SCL:1; SRVR:MN2PR12MB2974; H:SATLEXCHOV01.amd.com; FPR:; SPF:SoftFail; LANG:en; PTR:InfoDomainNonexistent; MX:1; A:1; X-Microsoft-Exchange-Diagnostics: 1; CO1NAM03FT057; 1:LLp4nFUCUjdRgO/V9LXQOAmPRTWlb7aWBg9eEF30Vezsh3l3svQZIWrOgUfS0nsgp6YQEBeL0us03NR84bjK4vTyWyLWBd7Mw9zb37jhZru47pRyb0B+5NJDkE/MVI9EiCgWnA2RKYgktKqfQq8/KA== X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6052ca0a-3dbd-49a9-2885-08d691c1efb1 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600110)(711020)(4605077)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060); SRVR:MN2PR12MB2974; X-MS-TrafficTypeDiagnostic: MN2PR12MB2974: X-Microsoft-Exchange-Diagnostics: 1; MN2PR12MB2974; 20:NaTxk5THSujJ3pIszIcxRjMiI5zwRnqvnai5GgeWwqQD16j02MGwrXzIClOIp38+qjtYDBLSJpHPmEL0jlnlqWPJ+QFgIv0AmxeJL+ezlu4ipNUdZUVDQU9Qvk8cyfskEJpjr5G+KF9iwmc4bCabhzTSO4smra0HzFNYtaYFFZT9AlKiBCsz6Q485HFytfS4TOdQ8vci4OhwaT7Quxg51Fr5Jp3lXAGx5cajX/+Q4PNV4sVIoW4EjMdWnEg8pv7eD+awLRfoIp4ygX/L0BXMZ21DGyorZ//yltE1X/itHNJgCWajpVATSCo9CYnD4dLWqMJwEJS1WhCkJnL/uHgMH17kbajmEydzpx4s+MpMARODCHZcMYpmC+krdh+vVyFZwUdUC7hOoQGo7mKEJ8fVo7DWibGUTeGoxqvo8IIYRwygSO3UejRHWhUFTz5vfyTDi/xu7XgZT2eAXgCEUjbPMshrHEMXv8S2N+gBbawhRhJ+Q6QpHIoMOoY8ITC5AokM X-Microsoft-Antispam-PRVS: X-Forefront-PRVS: 094700CA91 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; MN2PR12MB2974; 23:Ju7QkOFuqeHOOTtfJhxsz+7TRbPYRmT6lXNwLd6vm?= RnGFMxqWy2gpjIT6vhg91RC2++/vDjFskCR3To9Zq5l2UjYNrpWMx6yjvzBicGtw7k24Z/rUrF2KnU7OD/iT1CTjj/G0RFyhC6OJlvtAFKbCynt30D2va5dRahUkMGsks4VFA/QN/PkZ1NX7uJZQIHhd3xnW9e5UYi05vI6L7Ot+qn1bqgeN7JT5i9PiWR59Y9vKC4VbJBUaRNThFGrzuDDnt28mlnU0aP0D37XEoYeKzG9FdPk8NYdwcp3MA7lDOuBxEUWc2g1Pxvzxgx4qzVSVipoc0QnScc2me+FCjX0+gevb0AQr0SQr9J30/XcmoiHX3tNqllrIFMiT80mOrtOus5IN9cA8yA0o9dMGY4OLQHfPb4E48TFC6LTtUoCg4dJx4pbZcPzwaXqbSwOvbkCI3G0hT0v7BgU/Q7qWHnh6DqBilUarzK3LgSoFh/j/Q6t7PtXz4AgkCvExcrOImu1ZXwUsY/GpM6zs+M7FxYgr/ZCvg5W6hXeb82lYinTVKo8bzcWLzCPkHG45rOrLFl5/Bs1Axqfc/V4BiFxOndgzQI0dfQXRKemFfhJEfYjywVVIxRHKIcC7rKES5jyT/EPeJWSI0L3PB4VhF+ek3BJcSwlMiAnNCf+VcHGyQmBx1a4tcsl+/NrV1CaifiHOS178CrXTpnMQ01AhGBjKeyjqhY+KUHtaxPq7dY4N6+RP5KZRRWD0rMmmK+Ag+0ZhMhlNQdKnLRMVrQLcmmjPRfPITI/YQEHhypPIwUSfrU7nR3tZIMVP1js1yrO9rD4eHIbdahL5GPSPDut7rlPk30chjCyAcL+4EVtx0ZZLhBv0DTJnwoWQ3kytxjy4bDxm7jskrcAKZJryxqJEjbb14xmODwQ46KBnBNZeJGfGA2S/gBNqcz+J+uNZbM0s2aDBhxapldIEEqswD1HkguK9t6xWIiMoeON7HvMZ+qK0IqTnouUq3cxZ1R0N88QEEHYPEwyMilbC97hw3edDKAm8bkpvuoOBJsICKHWYoxjcPw/4DCseKnsnXTydxygXRIzouvilkB3ONSywE4jgF20UPpRadPU71Tah6u3k1wGG/vptyU= X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: WAzv7BxO6er44fvDRtxIPtywUCRwNji4PWJfEZea0FSdXddjh3ub/Vw7LgAU67wUUVq5NgRsQ3MXv4Dg2LBYEf3pGOn2QLHGwLPzgxCV941KmPJyd9NgjN+EWIxgFdPIjcP2ERQmUIzZzyt+D4d35kZ2cQvV9+Sc7DlhG2g+7jUKPkxds2gnarlVtj0svn/UXQWuyo60jdLteR6pH/Gxz+MSwOIS+etemTqJ7eQ6xQvZpecWJGzXtW9jh5oIdgEwxf6v8OhpU79XebihtsMN3sFsuwRGXE1+6jgcPJKJarQrgRak4iiT2BSfEaOHqGGYzk8MomuLme+8yPQvaT9m7v++yjvIaCf6g6fVlBbmkwr7m+QSCevg3DwEJCb/hYVjpc/OaPzsxdEUKi2q86BgRvl61Vl8RDAEeQ5HYooLdpg= X-Microsoft-Exchange-Diagnostics: 1; MN2PR12MB2974; 20:q6pud+kDxN+kFhiecZqmR1iCwHBNG/x511rnplRW3UbnrzCBI9DIu0T1NfCg9f4iqtB5GD8ao72uMtPXC/WHP/Kb1UYxIMuEmU5meVGzxro34c8S/2qdRyBWG5FrWmZDJJNgiwDyACRUiwhAyH6p9C/nrA1DaKLO4WbAzFv/G1+mZknyLx3V++mdahwZvzYM6NVu6UvQ9thPfR3EHMI2PJkqaAJ8G+eqACzbl9W5s1vP8c+8hqGVRHCmCBWlXfBl X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2019 14:45:45.3442 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6052ca0a-3dbd-49a9-2885-08d691c1efb1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXCHOV01.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB2974 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EuNQeFJ0Z6Os8u4d13LEKIx3JvohPUqVyBkaM0Y3ZJA=; b=gheqdoR18QVluQAg5rtsrSyiUkoqiCK8aeUFfISZKREAQArS9B+K81JNJrnt6kojzpx1TjCAqB6/QwOY135t+VfO12S6TbidoRe5Xnej16RQyLks+IixVb2IqBEcHpxtJeV9pB59XrIMoUa0V9vOl+0pzhyzsxYiVBAi+e4JDu4= X-Mailman-Original-Authentication-Results: spf=softfail (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; lists.freedesktop.org; dkim=none (message not signed) header.d=none;lists.freedesktop.org; dmarc=permerror action=none header.from=amd.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, nikola.cornij@amd.com, manasi.d.navare@intel.com, David Francis Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Native 420 and 422 transfer modes are new in DSC1.2 In these modes, each two pixels of a slice are treated as one pixel, so the slice width is half as large (round down) for the purposes of calucating the groups per line and chunk size in bytes In native 422 mode, each pixel has four components, so the mux component of a group is larger by one additional mux word and one additional component Now that there is native 422 support, the configuration option previously called enable422 is renamed to simple_422 to avoid confusion Signed-off-by: David Francis Reviewed-by: Harry Wentland Reviewed-by: Manasi Navare --- drivers/gpu/drm/drm_dsc.c | 31 +++++++++++++++++++++++-------- drivers/gpu/drm/i915/intel_vdsc.c | 4 ++-- include/drm/drm_dsc.h | 4 ++-- 3 files changed, 27 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c index 4b0e3c9c3ff8..9e675dd39a44 100644 --- a/drivers/gpu/drm/drm_dsc.c +++ b/drivers/gpu/drm/drm_dsc.c @@ -77,7 +77,7 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp, ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> DSC_PPS_MSB_SHIFT) | dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | - dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT | + dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT | dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; @@ -246,19 +246,34 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) unsigned long final_scale = 0; unsigned long rbs_min = 0; - /* Number of groups used to code each line of a slice */ - groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, - DSC_RC_PIXELS_PER_GROUP); + if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { + /* Number of groups used to code each line of a slice */ + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, + DSC_RC_PIXELS_PER_GROUP); - /* chunksize in Bytes */ - vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * - vdsc_cfg->bits_per_pixel, - (8 * 16)); + /* chunksize in Bytes */ + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * + vdsc_cfg->bits_per_pixel, + (8 * 16)); + } else { + /* Number of groups used to code each line of a slice */ + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, + DSC_RC_PIXELS_PER_GROUP); + + /* chunksize in Bytes */ + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * + vdsc_cfg->bits_per_pixel, + (8 * 16)); + } if (vdsc_cfg->convert_rgb) num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + (4 * vdsc_cfg->bits_per_component + 4) - 2); + else if (vdsc_cfg->native_422) + num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + + 3 * (4 * vdsc_cfg->bits_per_component) - 2; else num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + (4 * vdsc_cfg->bits_per_component + 4) + diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index c76cec8bfb74..7702c5c8b3f2 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -369,7 +369,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; /* Gen 11 does not support YCbCr */ - vdsc_cfg->enable422 = false; + vdsc_cfg->simple_422 = false; /* Gen 11 does not support VBR */ vdsc_cfg->vbr_enable = false; vdsc_cfg->block_pred_enable = @@ -496,7 +496,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, pps_val |= DSC_BLOCK_PREDICTION; if (vdsc_cfg->convert_rgb) pps_val |= DSC_COLOR_SPACE_CONVERSION; - if (vdsc_cfg->enable422) + if (vdsc_cfg->simple_422) pps_val |= DSC_422_ENABLE; if (vdsc_cfg->vbr_enable) pps_val |= DSC_VBR_ENABLE; diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index ad43494f1cc8..4e55e37943d7 100644 --- a/include/drm/drm_dsc.h +++ b/include/drm/drm_dsc.h @@ -70,10 +70,10 @@ struct drm_dsc_config { /* Slice Height */ u16 slice_height; /* - * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens + * Simple 4:2:2 mode (from PPS, 4:2:2 conversion happens * outside of DSC encode/decode algorithm) */ - bool enable422; + bool simple_422; /* Picture Width */ u16 pic_width; /* Picture Height */