Message ID | 20190226193609.9862-8-andrew.smirnov@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | tc358767 driver improvements | expand |
Hi Andrey, Thank you for the patch. On Tue, Feb 26, 2019 at 11:36:07AM -0800, Andrey Smirnov wrote: > Move common code converting clock rate to an appropriate constant and > configuring SYS_PLLPARAM register into a separate routine and convert > the rest of the code to use it. No functional change intended. > > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> > Cc: Archit Taneja <architt@codeaurora.org> > Cc: Andrzej Hajda <a.hajda@samsung.com> > Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> > Cc: Chris Healy <cphealy@gmail.com> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: dri-devel@lists.freedesktop.org > Cc: linux-kernel@vger.kernel.org Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > drivers/gpu/drm/bridge/tc358767.c | 50 +++++++++++++------------------ > 1 file changed, 20 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c > index 54ff95f66e30..227f14cd2d3d 100644 > --- a/drivers/gpu/drm/bridge/tc358767.c > +++ b/drivers/gpu/drm/bridge/tc358767.c > @@ -522,35 +522,42 @@ static int tc_stream_clock_calc(struct tc_data *tc) > return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768); > } > > -static int tc_aux_link_setup(struct tc_data *tc) > +static int tc_set_syspllparam(struct tc_data *tc) > { > unsigned long rate; > - u32 value; > - int ret; > - u32 dp_phy_ctrl; > + u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2; > > rate = clk_get_rate(tc->refclk); > switch (rate) { > case 38400000: > - value = REF_FREQ_38M4; > + pllparam |= REF_FREQ_38M4; > break; > case 26000000: > - value = REF_FREQ_26M; > + pllparam |= REF_FREQ_26M; > break; > case 19200000: > - value = REF_FREQ_19M2; > + pllparam |= REF_FREQ_19M2; > break; > case 13000000: > - value = REF_FREQ_13M; > + pllparam |= REF_FREQ_13M; > break; > default: > dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); > return -EINVAL; > } > > + return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam); > +} > + > +static int tc_aux_link_setup(struct tc_data *tc) > +{ > + int ret; > + u32 dp_phy_ctrl; > + > /* Setup DP-PHY / PLL */ > - value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; > - tc_write(SYS_PLLPARAM, value); > + ret = tc_set_syspllparam(tc); > + if (ret) > + return ret; > > dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN; > if (tc->link.base.num_lanes == 2) > @@ -811,7 +818,6 @@ static int tc_main_link_setup(struct tc_data *tc) > { > struct drm_dp_aux *aux = &tc->aux; > struct device *dev = tc->dev; > - unsigned int rate; > u32 dp_phy_ctrl; > int timeout; > u32 value; > @@ -828,25 +834,9 @@ static int tc_main_link_setup(struct tc_data *tc) > (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | > ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0)); > > - rate = clk_get_rate(tc->refclk); > - switch (rate) { > - case 38400000: > - value = REF_FREQ_38M4; > - break; > - case 26000000: > - value = REF_FREQ_26M; > - break; > - case 19200000: > - value = REF_FREQ_19M2; > - break; > - case 13000000: > - value = REF_FREQ_13M; > - break; > - default: > - return -EINVAL; > - } > - value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; > - tc_write(SYS_PLLPARAM, value); > + ret = tc_set_syspllparam(tc); > + if (ret) > + return ret; > > /* Setup Main Link */ > dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN; > -- > 2.20.1 >
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 54ff95f66e30..227f14cd2d3d 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -522,35 +522,42 @@ static int tc_stream_clock_calc(struct tc_data *tc) return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768); } -static int tc_aux_link_setup(struct tc_data *tc) +static int tc_set_syspllparam(struct tc_data *tc) { unsigned long rate; - u32 value; - int ret; - u32 dp_phy_ctrl; + u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2; rate = clk_get_rate(tc->refclk); switch (rate) { case 38400000: - value = REF_FREQ_38M4; + pllparam |= REF_FREQ_38M4; break; case 26000000: - value = REF_FREQ_26M; + pllparam |= REF_FREQ_26M; break; case 19200000: - value = REF_FREQ_19M2; + pllparam |= REF_FREQ_19M2; break; case 13000000: - value = REF_FREQ_13M; + pllparam |= REF_FREQ_13M; break; default: dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); return -EINVAL; } + return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam); +} + +static int tc_aux_link_setup(struct tc_data *tc) +{ + int ret; + u32 dp_phy_ctrl; + /* Setup DP-PHY / PLL */ - value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; - tc_write(SYS_PLLPARAM, value); + ret = tc_set_syspllparam(tc); + if (ret) + return ret; dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN; if (tc->link.base.num_lanes == 2) @@ -811,7 +818,6 @@ static int tc_main_link_setup(struct tc_data *tc) { struct drm_dp_aux *aux = &tc->aux; struct device *dev = tc->dev; - unsigned int rate; u32 dp_phy_ctrl; int timeout; u32 value; @@ -828,25 +834,9 @@ static int tc_main_link_setup(struct tc_data *tc) (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0)); - rate = clk_get_rate(tc->refclk); - switch (rate) { - case 38400000: - value = REF_FREQ_38M4; - break; - case 26000000: - value = REF_FREQ_26M; - break; - case 19200000: - value = REF_FREQ_19M2; - break; - case 13000000: - value = REF_FREQ_13M; - break; - default: - return -EINVAL; - } - value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; - tc_write(SYS_PLLPARAM, value); + ret = tc_set_syspllparam(tc); + if (ret) + return ret; /* Setup Main Link */ dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
Move common code converting clock rate to an appropriate constant and configuring SYS_PLLPARAM register into a separate routine and convert the rest of the code to use it. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Archit Taneja <architt@codeaurora.org> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org --- drivers/gpu/drm/bridge/tc358767.c | 50 +++++++++++++------------------ 1 file changed, 20 insertions(+), 30 deletions(-)