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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id 36sm801356edz.58.2019.03.06.14.41.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Mar 2019 14:41:27 -0800 (PST) From: Johan Jonker To: heiko@sntech.de Subject: [PATCH v4 4/4] dt-bindings: display: rockchip: add document for rk3066 hdmi Date: Wed, 6 Mar 2019 23:41:13 +0100 Message-Id: <20190306224113.24853-5-jbx6244@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190306224113.24853-1-jbx6244@gmail.com> References: <20190306224113.24853-1-jbx6244@gmail.com> X-Mailman-Approved-At: Thu, 07 Mar 2019 08:16:24 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lYw/rfpnmdx5PH54T9Dya+xirh/mbWltaop30jtIhxc=; b=BrIv6U2U3tq4P/QFhr3m+VGM/e62k41EH3dT5i520PqOf01CtztW+EgmZjnWNvag8q a8qSLoxDOcTV+ujRW1/FY3EPGiz7ZQN6QInVgf6IOLkvwXs8SIFgzMlYLULkkOB9tkdv FhdpFIQRhqdd824LhxkZWl1buIUcNpZt7QQoCNQbkUY8mnR2e0jb+UGYMTp5A7yXw5dX F1Fg+Uq/WMwahhpLdOE15BaBi+tXWJbXoHknYnjh/xLw+YAvsIc1hAb5kUBLBzgABflt KR3FYL47t7bN0irto1EreuC0HL4VRRrVwWdcd8YnqcQ3Bg8XDz+lycUURd5hkkWDKlcm 4XwA== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, airlied@linux.ie, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds a binding that describes the HDMI controller for rk3066. Signed-off-by: Johan Jonker Reviewed-by: Rob Herring --- .../display/rockchip/rockchip,rk3066-hdmi.txt | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.txt diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.txt new file mode 100644 index 000000000..d1ad31bca --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.txt @@ -0,0 +1,72 @@ +Rockchip specific extensions for rk3066 HDMI +============================================ + +Required properties: +- compatible: + "rockchip,rk3066-hdmi"; +- reg: + Physical base address and length of the controller's registers. +- clocks, clock-names: + Phandle to HDMI controller clock, name should be "hclk". +- interrupts: + HDMI interrupt number. +- power-domains: + Phandle to the RK3066_PD_VIO power domain. +- rockchip,grf: + This soc uses GRF regs to switch the HDMI TX input between vop0 and vop1. +- ports: + Contains one port node with two endpoints, numbered 0 and 1, + connected respectively to vop0 and vop1. + Contains one port node with one endpoint + connected to a hdmi-connector node. +- pinctrl-0, pinctrl-name: + Switch the iomux for the HPD/I2C pins to HDMI function. + +Example: + hdmi: hdmi@10116000 { + compatible = "rockchip,rk3066-hdmi"; + reg = <0x10116000 0x2000>; + interrupts = ; + clocks = <&cru HCLK_HDMI>; + clock-names = "hclk"; + power-domains = <&power RK3066_PD_VIO>; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vop0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop0_out_hdmi>; + }; + hdmi_in_vop1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vop1_out_hdmi>; + }; + }; + hdmi_out: port@1 { + reg = <1>; + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + }; + }; + +&pinctrl { + hdmi { + hdmi_hpd: hdmi-hpd { + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; + }; + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; +};