From patchwork Mon Mar 25 14:18:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 10869321 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F2E8A186D for ; Mon, 25 Mar 2019 14:18:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DF98A28FFE for ; Mon, 25 Mar 2019 14:18:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D460429019; Mon, 25 Mar 2019 14:18:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.6 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,URG_BIZ autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7527429025 for ; Mon, 25 Mar 2019 14:18:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6CDDC6E6B3; Mon, 25 Mar 2019 14:18:40 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1FC5C6E6A4 for ; Mon, 25 Mar 2019 14:18:34 +0000 (UTC) Received: by mail-wr1-x443.google.com with SMTP id r4so2670957wrq.8 for ; Mon, 25 Mar 2019 07:18:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yDypC/UmPJRFhJ57yj/6XU+1KJP8RA/zbaAQcFQyVBM=; b=qd9H20y9UEAgqRTU6krasvatnWrW4JrbDS0LWa6LBEj+eDdei1C7keY4pA1E4osBaA 4ezxEZDkf3QqOmCor9UhYtxPArsy4y5SOTrm+m8ANnxRLL1ek2oVRyjWEoAJbTvq87Q2 2mkXHoWbdBlEVhbAIYK1AXNOzlRv6QCJQ01eLvwYFYd89vGdhD8tG0oH+xiUW0nxQ1Ui nlqPj6WXxwRoeLdvL615v0OYAQTX8ysBh2oZacn9ox7jYjrz434nsKJxwxADjpYUP4Ur gvF98TQuRu1K8quPt9oTlD5crBjzFRFgbFobUQJXOYfaXKUPp3LgIXvHWRu3/K1c5tx7 CWPQ== X-Gm-Message-State: APjAAAW0W3/qef8vF4KgvY7uinn5CD3tRqUjZYZi4SuAZdWqndU1ke2r ao+AT84xprUkbLZC47q7O6G7hZjAeOimPw== X-Google-Smtp-Source: APXvYqycs+b9ISq2q/G1mMDsaLRRaZJaAEqJQ5OANgwPueOIt8hUR8mlYcjUboSz25ZC4A7uRHAM/g== X-Received: by 2002:a5d:68cf:: with SMTP id p15mr12181262wrw.301.1553523512498; Mon, 25 Mar 2019 07:18:32 -0700 (PDT) Received: from localhost.localdomain (176-150-251-154.abo.bbox.fr. [176.150.251.154]) by smtp.gmail.com with ESMTPSA id 132sm26976794wmd.30.2019.03.25.07.18.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 25 Mar 2019 07:18:31 -0700 (PDT) From: Neil Armstrong To: dri-devel@lists.freedesktop.org Subject: [PATCH 04/11] drm/meson: Add G12A Support for VIU setup Date: Mon, 25 Mar 2019 15:18:17 +0100 Message-Id: <20190325141824.21259-5-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190325141824.21259-1-narmstrong@baylibre.com> References: <20190325141824.21259-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yDypC/UmPJRFhJ57yj/6XU+1KJP8RA/zbaAQcFQyVBM=; b=i32RcdTZnAalHl7i9L6wGPhJgWMYWzvj9DXGJZ3VqlJi63NOPhYGGUGpJiVfb97qbi 5+E8+mp+mZSxZ309r/pjVj3Tn54j48cSpUsENCGz9kaKLeD7XOQwIfubkx2Xl3cTqzmy 95FUw++QLNvIuw24w1P7KpD3CKC1CTjiA0pvNcMzc05qg8jZYmpWsjdvX11z/y8q9M/v OsmTdWCVH/okHkQQNuBjm5cUv/R+XuQ4A7d6rLfkhHcoU0yfTRbz6qN+JbJ+WChrkZfW B3bFyLEluoRIfQmuHub0/NS9X7/PV6q0RxIKEiu1927EK2TSG0071FzUNT/9j8G7LpW6 stdQ== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Amlogic G12A SoC needs a different VIU setup code, handle it. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_viu.c | 72 ++++++++++++++++++++++++++++--- 1 file changed, 67 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c index ac0f3687e09a..0169c98b01c9 100644 --- a/drivers/gpu/drm/meson/meson_viu.c +++ b/drivers/gpu/drm/meson/meson_viu.c @@ -90,6 +90,34 @@ static int eotf_bypass_coeff[EOTF_COEFF_SIZE] = { EOTF_COEFF_RIGHTSHIFT /* right shift */ }; +void meson_viu_set_g12a_osd1_matrix(struct meson_drm *priv, int *m, + bool csc_on) +{ + /* VPP WRAP OSD1 matrix */ + writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), + priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1)); + writel(m[2] & 0xfff, + priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2)); + writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), + priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01)); + writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), + priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10)); + writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff), + priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); + writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff), + priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); + writel((m[11] & 0x1fff) << 16, + priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); + + writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff), + priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1)); + writel(m[20] & 0xfff, + priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2)); + + writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0, + priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); +} + void meson_viu_set_osd_matrix(struct meson_drm *priv, enum viu_matrix_sel_e m_select, int *m, bool csc_on) @@ -336,14 +364,24 @@ void meson_viu_init(struct meson_drm *priv) if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) meson_viu_load_matrix(priv); + else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) + meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff, + true); /* Initialize OSD1 fifo control register */ reg = BIT(0) | /* Urgent DDR request priority */ - (4 << 5) | /* hold_fifo_lines */ - (3 << 10) | /* burst length 64 */ - (32 << 12) | /* fifo_depth_val: 32*8=256 */ - (2 << 22) | /* 4 words in 1 burst */ - (2 << 24); + (4 << 5); /* hold_fifo_lines */ + if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) + reg |= (1 << 10) | /* burst length 32 */ + (32 << 12) | /* fifo_depth_val: 32*8=256 */ + (2 << 22) | /* 4 words in 1 burst */ + (2 << 24) | + (1 << 31); + else + reg |= (3 << 10) | /* burst length 64 */ + (32 << 12) | /* fifo_depth_val: 32*8=256 */ + (2 << 22) | /* 4 words in 1 burst */ + (2 << 24); writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT)); @@ -369,6 +407,30 @@ void meson_viu_init(struct meson_drm *priv) writel_relaxed(0x00FF00C0, priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE)); + if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { + writel_relaxed(4 << 29 | + 1 << 27 | + 1 << 26 | /* blend_din0 input to blend0 */ + 1 << 25 | /* blend1_dout to blend2 */ + 1 << 24 | /* blend1_din3 input to blend1 */ + 1 << 20 | + 0 << 16 | + 1, + priv->io_base + _REG(VIU_OSD_BLEND_CTRL)); + writel_relaxed(3 << 8 | + 1 << 20, + priv->io_base + _REG(OSD1_BLEND_SRC_CTRL)); + writel_relaxed(1 << 20, + priv->io_base + _REG(OSD2_BLEND_SRC_CTRL)); + writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); + writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL)); + writel_relaxed(0, + priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_DATA0)); + writel_relaxed(0, + priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_ALPHA)); + writel_bits_relaxed(0x3 << 2, 0x3 << 2, + priv->io_base + _REG(DOLBY_PATH_CTRL)); + } priv->viu.osd1_enabled = false; priv->viu.osd1_commit = false;