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a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zXz6xGHG2Vq2PrV41mfgqIlJbWXMBQx9Ur9HMck8sbU=; b=x5lZOqD+AEgjGUyR1WTwAPMyJJNXiK2Cn6UqUYl0wpl89D19TZeFrnPKM+Y8hAZwIA482GID9hakByKakSrLbBF2LDMv+V7yAw1h1xhTZrLbNwx6mp5jJTT4mMbPSk7LX1MHvIQiBsHpZIBOuJgBiBLyWa0aFiXLTBSs7z2AcSQ= X-Mailman-Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=wen.he_1@nxp.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Wen He Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP When we running DDR benchmark test will able to observed flicker issue in 4k@60 resolution on monitor. In LS1028A SoC, need increasing DP500 priority to avoid that issue. Signed-off-by: Wen He --- drivers/gpu/drm/arm/malidp_hw.c | 13 +++++++++++++ drivers/gpu/drm/arm/malidp_regs.h | 8 ++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index 8df12e9a33bb..a5263488eb02 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -378,6 +378,19 @@ static void malidp500_modeset(struct malidp_hw_device *hwdev, struct videomode * malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC); else malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC); + +#ifdef CONFIG_ARCH_LAYERSCAPE + /* Setting QoS for 4k resolution to avoid flicker issue */ + if (mode->hactive == 3840 + && mode->vactive == 2160) + malidp_hw_setbits(hwdev, GREEN_ARQOS_CONFIG + | RED_ARQOS_CONFIG, MALIDP500_RQOS_QUALITY); + else + malidp_hw_clearbits(hwdev, GREEN_ARQOS_CONFIG + | RED_ARQOS_CONFIG, MALIDP500_RQOS_QUALITY); + + malidp_hw_setbits(hwdev, CONFIG_VALID, MALIDP500_CONFIG_VALID); +#endif } int malidp_format_get_bpp(u32 fmt) diff --git a/drivers/gpu/drm/arm/malidp_regs.h b/drivers/gpu/drm/arm/malidp_regs.h index a0dd6e1676a8..8dcf7e9f46ce 100644 --- a/drivers/gpu/drm/arm/malidp_regs.h +++ b/drivers/gpu/drm/arm/malidp_regs.h @@ -213,6 +213,14 @@ #define MALIDP500_DC_IRQ_BASE 0x00f00 #define MALIDP500_CONFIG_VALID 0x00f00 #define MALIDP500_CONFIG_ID 0x00fd4 +#ifdef CONFIG_ARCH_LAYERSCAPE +#define MALIDP500_RQOS_QUALITY 0x00500 +/* Increasing QoS level signal */ +#define GREEN_ARQOS_CONFIG (0xd << 28) +/* Close to underflow QoS level signal */ +#define RED_ARQOS_CONFIG (0xd << 12) +#define CONFIG_VALID 0x3 +#endif /* register offsets and bits specific to DP550/DP650 */ #define MALIDP550_ADDR_SPACE_SIZE 0x10000