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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id a69sm4022560pfa.81.2019.05.30.09.00.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 May 2019 09:00:25 -0700 (PDT) From: Jeffrey Hugo To: robdclark@gmail.com, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH 1/4] dt-bindings: msm/dsi: Add 10nm phy for msm8998 compatible Date: Thu, 30 May 2019 09:00:23 -0700 Message-Id: <20190530160023.2773-1-jeffrey.l.hugo@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190530155909.2718-1-jeffrey.l.hugo@gmail.com> References: <20190530155909.2718-1-jeffrey.l.hugo@gmail.com> X-Mailman-Approved-At: Thu, 30 May 2019 16:46:45 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JlasCBadKVSsXNr9CWB0njdLgCAXoVvqrNuDEFbuiAk=; b=GGmvQfnjEYqg8qQyb2/5A1vSa5dD9qVfe8yOwyW2rD/Y8VqE6iaViUCuy/BFehmPVJ PjpbhjyrSODquqB6uzFDXx8DgOgey45RoPlY2fqhz80ezGwluIbikPcA104eRL/U3p0O s7cELqrWxaZedQ99dD3wcl3EUVZyWX5l7N6FwYcxRkEfxy1jUWvObhPB9WPCcD0v94S3 uWr5tHcjTcD3TG3nnSoRFhlHTWakjZPLtwZkPI5ayGWTRxuAomVKxg1dWzRt+vmnwbVX 1mTYq/EfeuLTBXoihmdBHQBnNUWIeNG579eMNQmArE8MU7SCGIQtFF4FkP/CVLYe6Avq cb5A== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, marc.w.gonzalez@free.fr, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Jeffrey Hugo , linux-kernel@vger.kernel.org, abhinavk@codeaurora.org, bjorn.andersson@linaro.org, sibis@codeaurora.org, freedreno@lists.freedesktop.org, chandanu@codeaurora.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The DSI phy on MSM8998 is a 10nm design like SDM845, however it has some slightly different quirks which need to be handled by drivers. Provide a separate compatible to assist in handling the specifics. Signed-off-by: Jeffrey Hugo --- Documentation/devicetree/bindings/display/msm/dsi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 9ae946942720..af95586c898f 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -88,6 +88,7 @@ Required properties: * "qcom,dsi-phy-28nm-8960" * "qcom,dsi-phy-14nm" * "qcom,dsi-phy-10nm" + * "qcom,dsi-phy-10nm-8998" - reg: Physical base address and length of the registers of PLL, PHY. Some revisions require the PHY regulator base address, whereas others require the PHY lane base address. See below for each PHY revision.