| Message ID | 20190626132427.12615-1-colin.king@canonical.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [next[ drm/amd/display: fix a couple of spelling mistakes | expand |
Hi Colin, On Wed, 26 Jun 2019 at 14:24, Colin King <colin.king@canonical.com> wrote: > There are a couple of spelling mistakes in dm_error messages and > a comment. Fix these. Whilst there, you might fix the '[next[' typo in the commit message. Cheers, Daniel
On 26/06/2019 14:25, Daniel Stone wrote: > Hi Colin, > > On Wed, 26 Jun 2019 at 14:24, Colin King <colin.king@canonical.com> wrote: >> There are a couple of spelling mistakes in dm_error messages and >> a comment. Fix these. > > Whilst there, you might fix the '[next[' typo in the commit message. Ugh, fickle fingers. Maybe the upstream devs will fix that before applying... > > Cheers, > Daniel >
On Wed, Jun 26, 2019 at 9:32 AM Colin Ian King <colin.king@canonical.com> wrote: > > On 26/06/2019 14:25, Daniel Stone wrote: > > Hi Colin, > > > > On Wed, 26 Jun 2019 at 14:24, Colin King <colin.king@canonical.com> wrote: > >> There are a couple of spelling mistakes in dm_error messages and > >> a comment. Fix these. > > > > Whilst there, you might fix the '[next[' typo in the commit message. > > Ugh, fickle fingers. Maybe the upstream devs will fix that before > applying... Fixed up and applied. Thanks, Alex > > > > > > Cheers, > > Daniel > > > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c index be49fc7f4abe..ffd0014ec3b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c @@ -126,7 +126,7 @@ static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it. * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices. - * The value below is the absolute maximum value. The actual througput may be lower, but it'll always + * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always * be sufficient to process the input pixel rate fed into a single DSC engine. */ dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 77e7a0f8a527..ef5f84a144c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -47,7 +47,7 @@ static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_bl *buff_block_size = 64 * 1024; break; default: { - dm_error("%s: DPCD DSC buffer size not recoginzed.\n", __func__); + dm_error("%s: DPCD DSC buffer size not recognized.\n", __func__); return false; } } @@ -63,7 +63,7 @@ static bool dsc_line_buff_depth_from_dpcd(int dpcd_line_buff_bit_depth, int *lin else if (dpcd_line_buff_bit_depth == 8) *line_buff_bit_depth = 8; else { - dm_error("%s: DPCD DSC buffer depth not recoginzed.\n", __func__); + dm_error("%s: DPCD DSC buffer depth not recognized.\n", __func__); return false; } @@ -123,7 +123,7 @@ static bool dsc_throughput_from_dpcd(int dpcd_throughput, int *throughput) *throughput = 1000; break; default: { - dm_error("%s: DPCD DSC througput mode not recoginzed.\n", __func__); + dm_error("%s: DPCD DSC throughput mode not recognized.\n", __func__); return false; } } @@ -152,7 +152,7 @@ static bool dsc_bpp_increment_div_from_dpcd(int bpp_increment_dpcd, uint32_t *bp *bpp_increment_div = 1; break; default: { - dm_error("%s: DPCD DSC bits-per-pixel increment not recoginzed.\n", __func__); + dm_error("%s: DPCD DSC bits-per-pixel increment not recognized.\n", __func__); return false; } }