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Wed, 21 Aug 2019 20:01:40 +0000 Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Received: from SATLEXCHOV02.amd.com (165.204.84.17) by CO1NAM03FT063.mail.protection.outlook.com (10.152.81.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2178.16 via Frontend Transport; Wed, 21 Aug 2019 20:01:40 +0000 Received: from localhost.localdomain (10.180.168.240) by SATLEXCHOV02.amd.com (10.181.40.72) with Microsoft SMTP Server id 14.3.389.1; Wed, 21 Aug 2019 15:01:34 -0500 From: David Francis To: , Subject: [PATCH v3 02/16] Revert "drm/amd/display: navi10 bring up skip dsc encoder config" Date: Wed, 21 Aug 2019 16:01:15 -0400 Message-ID: <20190821200129.11575-3-David.Francis@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821200129.11575-1-David.Francis@amd.com> References: <20190821200129.11575-1-David.Francis@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:165.204.84.17; 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a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ad5QdkLef/A+rdIQQWP3FTj0kRa3P6DtHyGuaj8rCCU=; b=CNteeKsxvyxPXrQWbJkxt1ZMOHKX9HkcHfWbXF35samAYGQc61m1T7rOE6RYpoIIxtEABzaldX0kRvrZHi/6TJq0TaO1jy7QuBSnkIl5GALgcmBeydtjimWhVPaDMD5R1hPJruYiXjAc28J+tMRr0z0rSnIh1frs3YNRdTZBsKk= X-Mailman-Original-Authentication-Results: spf=none (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; lists.freedesktop.org; dkim=none (message not signed) header.d=none;lists.freedesktop.org; dmarc=permerror action=none header.from=amd.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Francis Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This reverts commit 5f2fd347eeff7d4ce271920efd47baaa18fe968c. Re-enable enc2_dp_set_dsc_config. This function caused warnings due to missing register definitions. With the registers added, this now works Signed-off-by: David Francis Reviewed-by: Roman Li Reviewed-by: Harry Wentland Reviewed-by: Nicholas Kazlauskas --- .../gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c index 6d54942ab98b..a4e67286cdad 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c @@ -277,14 +277,6 @@ static void enc2_dp_set_dsc_config(struct stream_encoder *enc, uint32_t dsc_slice_width) { struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t dsc_value = 0; - - dsc_value = REG_READ(DP_DSC_CNTL); - - /* dsc disable skip */ - if ((dsc_value & 0x3) == 0x0) - return; - REG_UPDATE_2(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode,