@@ -189,8 +189,8 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
int slots = 0;
bool ret;
int clock;
- int bpp = 0;
int pbn = 0;
+ int pbn_per_timeslot, bpp = 0;
aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
@@ -234,11 +234,18 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
bpp = bpp * 3;
- /* TODO need to know link rate */
-
- pbn = drm_dp_calc_pbn_mode(clock, bpp);
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (stream->timing.flags.DSC)
+ pbn = drm_dp_calc_pbn_mode_dsc(clock,
+ stream->timing.dsc_cfg.bits_per_pixel);
+ else
+#endif
+ pbn = drm_dp_calc_pbn_mode(clock, bpp);
- slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
+ /* Convert kilobits per second / 64 (for 64 timeslots) to pbn (54/64 megabytes per second) */
+ pbn_per_timeslot = dc_link_bandwidth_kbps(
+ stream->link, dc_link_get_link_cap(stream->link)) / (8 * 1000 * 54);
+ slots = DIV_ROUND_UP(pbn, pbn_per_timeslot);
ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
if (!ret)
We were using drm helpers to convert a timing into its bandwidth, its bandwidth into pbn, and its pbn into timeslots These helpers -Did not take DSC timings into account -Used the link rate and lane count of the link's aux device, which are not the same as the link's current cap -Did not take FEC into account (FEC reduces the PBN per timeslot) For converting timing into PBN, use the new function drm_dp_calc_pbn_mode_dsc that handles the DSC case For converting PBN into time slots, amdgpu doesn't use the 'correct' atomic method (drm_dp_atomic_find_vcpi_slots), so don't add a new helper to cover our approach. Use the same means of calculating pbn per time slot as the DSC code. Cc: Jerry Zuo <Jerry.Zuo@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: David Francis <David.Francis@amd.com> --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-)