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Wed, 21 Aug 2019 20:01:51 +0000 Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Received: from SATLEXCHOV02.amd.com (165.204.84.17) by CO1NAM03FT063.mail.protection.outlook.com (10.152.81.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2178.16 via Frontend Transport; Wed, 21 Aug 2019 20:01:51 +0000 Received: from localhost.localdomain (10.180.168.240) by SATLEXCHOV02.amd.com (10.181.40.72) with Microsoft SMTP Server id 14.3.389.1; Wed, 21 Aug 2019 15:01:38 -0500 From: David Francis To: , Subject: [PATCH v3 07/16] drm/amd/display: Use correct helpers to compute timeslots Date: Wed, 21 Aug 2019 16:01:20 -0400 Message-ID: <20190821200129.11575-8-David.Francis@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821200129.11575-1-David.Francis@amd.com> References: <20190821200129.11575-1-David.Francis@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:165.204.84.17; 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a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hg7fJjSOJUwUU2Hv3QG70YES6kZtea17elag+nMVXYg=; b=wPBS4P47/hk70eyeQKOe5YTBKWC6lf5yyX+ACJWvUqRLyym5ub76DMomnnq0NlvWX9hnmXL4FDuM9e9atDE30HtVGMkwC0ChIno6U7Eo9NG+3+ukfybh11Vw1Uu0uN2qqiu8IjbEI6KqPPe+iULiR42xniBSndRkGDH2idWDIVw= X-Mailman-Original-Authentication-Results: spf=none (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; lists.freedesktop.org; dkim=none (message not signed) header.d=none;lists.freedesktop.org; dmarc=permerror action=none header.from=amd.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Francis , Jerry Zuo , Nicholas Kazlauskas Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" We were using drm helpers to convert a timing into its bandwidth, its bandwidth into pbn, and its pbn into timeslots These helpers -Did not take DSC timings into account -Used the link rate and lane count of the link's aux device, which are not the same as the link's current cap -Did not take FEC into account (FEC reduces the PBN per timeslot) For converting timing into PBN, use the new function drm_dp_calc_pbn_mode_dsc that handles the DSC case For converting PBN into time slots, amdgpu doesn't use the 'correct' atomic method (drm_dp_atomic_find_vcpi_slots), so don't add a new helper to cover our approach. Use the same means of calculating pbn per time slot as the DSC code. Cc: Jerry Zuo Cc: Nicholas Kazlauskas Signed-off-by: David Francis --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 5f2c315b18ba..716d6577cdbd 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -189,8 +189,8 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( int slots = 0; bool ret; int clock; - int bpp = 0; int pbn = 0; + int pbn_per_timeslot, bpp = 0; aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; @@ -234,11 +234,18 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( bpp = bpp * 3; - /* TODO need to know link rate */ - - pbn = drm_dp_calc_pbn_mode(clock, bpp); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (stream->timing.flags.DSC) + pbn = drm_dp_calc_pbn_mode_dsc(clock, + stream->timing.dsc_cfg.bits_per_pixel); + else +#endif + pbn = drm_dp_calc_pbn_mode(clock, bpp); - slots = drm_dp_find_vcpi_slots(mst_mgr, pbn); + /* Convert kilobits per second / 64 (for 64 timeslots) to pbn (54/64 megabytes per second) */ + pbn_per_timeslot = dc_link_bandwidth_kbps( + stream->link, dc_link_get_link_cap(stream->link)) / (8 * 1000 * 54); + slots = DIV_ROUND_UP(pbn, pbn_per_timeslot); ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots); if (!ret)