From patchwork Tue Sep 3 01:39:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 11127105 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 97EFE1395 for ; Tue, 3 Sep 2019 01:39:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 75C74217D7 for ; Tue, 3 Sep 2019 01:39:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 75C74217D7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2528B89951; Tue, 3 Sep 2019 01:39:19 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTP id D6CD789951 for ; Tue, 3 Sep 2019 01:39:17 +0000 (UTC) X-UUID: 6d6db5c5ebc44cf2b5ad3837c9d4759b-20190903 X-UUID: 6d6db5c5ebc44cf2b5ad3837c9d4759b-20190903 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1775787851; Tue, 03 Sep 2019 09:39:12 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 Sep 2019 09:39:12 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 3 Sep 2019 09:39:12 +0800 From: Bibby Hsieh To: David Airlie , Matthias Brugger , Daniel Vetter , , Subject: [PATCH] arm64: dts: mt8183: Add gce setting in display node Date: Tue, 3 Sep 2019 09:39:10 +0800 Message-ID: <20190903013910.30225-1-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drinkcat@chromium.org, Yongqiang Niu , linux-kernel@vger.kernel.org, tfiga@chromium.org, Thierry Reding , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In order to use GCE function, we need add some informations into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events). Signed-off-by: Bibby Hsieh Signed-off-by: Yongqiang Niu --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5616d158a4fa..b7d294c1c5b4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -485,6 +485,11 @@ compatible = "mediatek,mt8183-display"; reg = <0 0x14000000 0 0x1000>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + mediatek,gce-events = , + ; }; ovl0: ovl@14008000 { @@ -494,6 +499,7 @@ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; }; ovl_2l0: ovl@14009000 { @@ -503,6 +509,7 @@ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; }; ovl_2l1: ovl@1400a000 { @@ -512,6 +519,7 @@ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; }; rdma0: rdma@1400b000 { @@ -522,6 +530,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA0>; mediatek,larb = <&larb0>; mediatek,rdma_fifo_size = <5>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; }; rdma1: rdma@1400c000 { @@ -532,6 +541,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA1>; mediatek,larb = <&larb0>; mediatek,rdma_fifo_size = <2>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; color0: color@1400e000 { @@ -541,6 +551,7 @@ interrupts = ; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; ccorr0: ccorr@1400f000 { @@ -549,6 +560,7 @@ interrupts = ; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; }; aal0: aal@14010000 { @@ -558,6 +570,7 @@ interrupts = ; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; }; gamma0: gamma@14011000 { @@ -567,6 +580,7 @@ interrupts = ; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; }; dither0: dither@14012000 { @@ -575,6 +589,7 @@ interrupts = ; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; }; mutex: mutex@14016000 {