From patchwork Wed Sep 18 12:24:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 11150257 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B711B13BD for ; Wed, 18 Sep 2019 12:25:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9F7AD21927 for ; Wed, 18 Sep 2019 12:25:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9F7AD21927 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E96B6EF1C; Wed, 18 Sep 2019 12:25:04 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailgw01.mediatek.com (unknown [1.203.163.78]) by gabe.freedesktop.org (Postfix) with ESMTP id 0280A6EF1C for ; Wed, 18 Sep 2019 12:25:01 +0000 (UTC) X-UUID: 9d3bc28d9f83484a904cdbd2a09b560c-20190918 X-UUID: 9d3bc28d9f83484a904cdbd2a09b560c-20190918 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 765747428; Wed, 18 Sep 2019 20:24:51 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 18 Sep 2019 20:24:49 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (172.27.4.253) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 18 Sep 2019 20:24:49 +0800 From: Jitao Shi To: Sam Ravnborg , David Airlie , Daniel Vetter , , Subject: [PATCH v6 6/8] drm/panel: support for boe, tv101wum-n53 wuxga dsi video mode panel Date: Wed, 18 Sep 2019 20:24:20 +0800 Message-ID: <20190918122422.17339-7-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918122422.17339-1-jitao.shi@mediatek.com> References: <20190918122422.17339-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 68ABDFB39E602B01DE4F249EF7E717C1950CB5F0A3727FEBEB945C81461B806A2000:8 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jitao Shi , srv_heupstream@mediatek.com, stonea168@163.com, cawa.cheng@mediatek.com, linux-mediatek@lists.infradead.org, yingjoe.chen@mediatek.com, eddie.huang@mediatek.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Boe,tv101wum-n53's connector is same as boe,tv101wum-nl6. The most codes can be reuse. So boe,tv101wum-n53 and boe,tv101wum-nl6 use one driver file. Add the different parts in driver data. Signed-off-by: Jitao Shi --- .../gpu/drm/panel/panel-boe-tv101wum-nl6.c | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c index f80974778360..c757035ac09c 100644 --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -621,6 +621,34 @@ static const struct panel_desc auo_kd101n80_45na_desc = { .discharge_on_disable = true, }; +static const struct drm_display_mode boe_tv101wum_n53_default_mode = { + .clock = 159833, + .hdisplay = 1200, + .hsync_start = 1200 + 114, + .hsync_end = 1200 + 114 + 10, + .htotal = 1200 + 114 + 10 + 40, + .vdisplay = 1920, + .vsync_start = 1920 + 19, + .vsync_end = 1920 + 19 + 4, + .vtotal = 1920 + 19 + 4 + 10, + .vrefresh = 60, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct panel_desc boe_tv101wum_n53_desc = { + .modes = &boe_tv101wum_n53_default_mode, + .bpc = 8, + .size = { + .width_mm = 135, + .height_mm = 216, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init_cmds = boe_init_cmd, +}; + static int boe_panel_get_modes(struct drm_panel *panel) { struct boe_panel *boe = to_boe_panel(panel); @@ -747,6 +775,9 @@ static const struct of_device_id boe_of_match[] = { { .compatible = "auo,kd101n80-45na", .data = &auo_kd101n80_45na_desc }, + { .compatible = "boe,tv101wum-n53", + .data = &boe_tv101wum_n53_desc + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, boe_of_match);