From patchwork Mon Sep 30 22:47:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 11167711 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 421EE13BD for ; Mon, 30 Sep 2019 22:47:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2A5C32086A for ; Mon, 30 Sep 2019 22:47:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2A5C32086A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B81C6E506; Mon, 30 Sep 2019 22:47:11 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D43C6E505; Mon, 30 Sep 2019 22:47:09 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Sep 2019 15:47:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,568,1559545200"; d="scan'208";a="184992010" Received: from mdroper-desk1.fm.intel.com ([10.1.27.135]) by orsmga008.jf.intel.com with ESMTP; 30 Sep 2019 15:47:09 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v7 3/3] drm/i915: Add background color hardware readout and state check Date: Mon, 30 Sep 2019 15:47:07 -0700 Message-Id: <20190930224707.14904-4-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190930224707.14904-1-matthew.d.roper@intel.com> References: <20190930224707.14904-1-matthew.d.roper@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" We should support readout and verification of crtc background color as we do with other pipe state. Note that our hardware holds less bits of precision than the CRTC state allows, so we need to take care to only verify the most significant bits of the color after performing readout. At boot time the pipe color is already sanitized to full black as required by ABI, so the new readout here won't break that requirement. Suggested-by: Ville Syrjälä Cc: Ville Syrjälä Signed-off-by: Matt Roper Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 32 ++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 78e64c62f34f..516e2927566a 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10453,6 +10453,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf; enum intel_display_power_domain power_domain; u64 power_domain_mask; + u32 bgcolor; bool active; intel_crtc_init_scalers(crtc, pipe_config); @@ -10565,6 +10566,15 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->pixel_multiplier = 1; } + if (INTEL_GEN(dev_priv) >= 9) { + bgcolor = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe)); + pipe_config->base.bgcolor = + drm_argb(10, 0xFFFF, + bgcolor >> 20 & 0x3FF, + bgcolor >> 10 & 0x3FF, + bgcolor & 0x3FF); + } + out: for_each_power_domain(power_domain, power_domain_mask) intel_display_power_put(dev_priv, @@ -12245,6 +12255,10 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, if (plane->pipe == crtc->pipe) intel_dump_plane_state(plane_state); } + + if (INTEL_GEN(dev_priv) >= 9) + DRM_DEBUG_KMS("background color: %llx\n", + pipe_config->base.bgcolor); } static bool check_digital_port_conflicts(struct intel_atomic_state *state) @@ -12639,6 +12653,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, } \ } while (0) +#define PIPE_CONF_CHECK_LLX_MASKED(name, mask) do { \ + if ((current_config->name & mask) != (pipe_config->name & mask)) { \ + pipe_config_mismatch(fastset, __stringify(name), \ + "(expected 0x%016llx, found 0x%016llx)\n", \ + current_config->name & mask, \ + pipe_config->name & mask); \ + ret = false; \ + } \ +} while (0) + #define PIPE_CONF_CHECK_I(name) do { \ if (current_config->name != pipe_config->name) { \ pipe_config_mismatch(fastset, __stringify(name), \ @@ -12945,6 +12969,14 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_INFOFRAME(hdmi); PIPE_CONF_CHECK_INFOFRAME(drm); + /* + * Hardware only holds top 10 bits of each color component; ignore + * bottom six bits (and all of alpha) when comparing against readout. + */ + if (INTEL_GEN(dev_priv) >= 9) + PIPE_CONF_CHECK_LLX_MASKED(base.bgcolor, 0x0000FFC0FFC0FFC0); + +#undef PIPE_CONF_CHECK_LLX_MASKED #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I #undef PIPE_CONF_CHECK_BOOL