From patchwork Tue Oct 15 11:33:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11190171 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8D28D912 for ; Tue, 15 Oct 2019 11:33:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 75C9621848 for ; Tue, 15 Oct 2019 11:33:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 75C9621848 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 220696E7AF; Tue, 15 Oct 2019 11:33:28 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6A3786E7AD for ; Tue, 15 Oct 2019 11:33:23 +0000 (UTC) Received: by mail-wm1-x344.google.com with SMTP id m18so19909333wmc.1 for ; Tue, 15 Oct 2019 04:33:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KGLJVsNqev2Pu0SrD3On1A2o4/VJ1lpv7UIRH8Pz9IM=; b=FzwObAaOKTuzLT7ZND+mkPItrXySfxN5E5yyGzufg56jeuoTljSjoLIJOVHVVM6R/E FxTX5aHKLeys2/MIJhwto13DUTL8dHJ8ReHVFqLbnwTn6K+xxDBb3HKazw9evuZvAmLb pn8XSRM/r/p3tsiPOk30oGlL7poXd0EbAEpL5SIU+jpBpA00nMQ5ZFdD5KJDp/8Sc74e swqkOzT2gMSOPuBGBK1VVE0zjRLErMAx9MTYmtwHEUJyqBoPWepKelrkGH4DSWCIXEeC 1BMw76o2bKKc3wXLMacbN6+kDFBxCTL2/eaLCT/HUHIcpWY59JdSsq0qCCXoC0RCbv5U +BMQ== X-Gm-Message-State: APjAAAUvZli4vUUMzAy0Kd7YErFzX1djvyoOKqAZyCfWhoOmYacd1K01 5hWTnj1/ygfINfHyimfrQJQWRhpk8OZa2A== X-Google-Smtp-Source: APXvYqzZdAXaUpGAPplnWQNtzhFSJwWdMt0J26CbY0jWOEEM95qMYh3DeBdhVnwqT9/M00AH/gVeTQ== X-Received: by 2002:a7b:ce12:: with SMTP id m18mr18640193wmc.108.1571139201527; Tue, 15 Oct 2019 04:33:21 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id 63sm32395096wri.25.2019.10.15.04.33.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 04:33:21 -0700 (PDT) From: Neil Armstrong To: dri-devel@lists.freedesktop.org Subject: [PATCH 3/3] drm/meson: use RDMA to reconfigure AFBC on vsync Date: Tue, 15 Oct 2019 13:33:17 +0200 Message-Id: <20191015113317.8870-4-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20191015113317.8870-1-narmstrong@baylibre.com> References: <20191015113317.8870-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KGLJVsNqev2Pu0SrD3On1A2o4/VJ1lpv7UIRH8Pz9IM=; b=l5IXnpYGo3Y6+5Ol9NmoMngdaTzKCwQ1j6TfH4/PaDlVfRX0bKuSvifFb4BCW2dnJn C/Vw0/attmUWpVUPr7UGHwndNl4jgHWjquQ0NZq4DtuxqJT0khDV+sjIeZRHQVPUbpsX j8QCKdzuEL9w9pijBhzfAVm46CEKGO9k2YT3hMKEdnfd7LmvRaGKubWu9BZjWCx9lMtQ LhKOIH1JcgKdAQN1jNLAkU16iHE98x0DT2B/wYafaTaRNrJFBnrlOsj2JTwIpFKagYu8 ZyMp0qQrGsEkp3IvoPpo8EwlxhLdUWornqgjGUmi4UBLdbBRKjg0U9FUsMOLH5qBv7sm K3gg== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khilman@baylibre.com, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The VPU embeds a "Register DMA" that can write a sequence of registers on the VPU AHB bus, either manually or triggered by an internal IRQ event like VSYNC or a line input counter. The RDMA is used here to reset and program the AFBC decoder unit on each vsync without involving the interrupt handler that can be masked for a long period of time, producing display glitches. For this we use the meson_rdma_writel_sync() which adds the register write tuple (VPU register offset and register value) to the RDMA buffer and write the value to the HW. When enabled, the RDMA is enabled to rewritte the same sequence at the next VSYNC event, until a new buffer is committed to the OSD plane. The the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder doesn't need a reset/reprogram at each vsync. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_crtc.c | 27 ++----- drivers/gpu/drm/meson/meson_osd_afbcd.c | 100 ++++++++++++++---------- 2 files changed, 64 insertions(+), 63 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c index d28efd0dbf11..8e0cf03e45eb 100644 --- a/drivers/gpu/drm/meson/meson_crtc.c +++ b/drivers/gpu/drm/meson/meson_crtc.c @@ -23,6 +23,7 @@ #include "meson_registers.h" #include "meson_venc.h" #include "meson_viu.h" +#include "meson_rdma.h" #include "meson_vpp.h" #include "meson_osd_afbcd.h" @@ -39,8 +40,6 @@ struct meson_crtc { void (*enable_osd1_afbc)(struct meson_drm *priv); void (*disable_osd1_afbc)(struct meson_drm *priv); unsigned int viu_offset; - bool vsync_forced; - bool vsync_disabled; }; #define to_meson_crtc(x) container_of(x, struct meson_crtc, base) @@ -51,7 +50,6 @@ static int meson_crtc_enable_vblank(struct drm_crtc *crtc) struct meson_crtc *meson_crtc = to_meson_crtc(crtc); struct meson_drm *priv = meson_crtc->priv; - meson_crtc->vsync_disabled = false; meson_venc_enable_vsync(priv); return 0; @@ -62,10 +60,7 @@ static void meson_crtc_disable_vblank(struct drm_crtc *crtc) struct meson_crtc *meson_crtc = to_meson_crtc(crtc); struct meson_drm *priv = meson_crtc->priv; - if (!meson_crtc->vsync_forced) { - meson_crtc->vsync_disabled = true; - meson_venc_disable_vsync(priv); - } + meson_venc_disable_vsync(priv); } static const struct drm_crtc_funcs meson_crtc_funcs = { @@ -368,10 +363,11 @@ void meson_crtc_irq(struct meson_drm *priv) if (meson_crtc->enable_osd1) meson_crtc->enable_osd1(priv); - if (priv->viu.osd1_afbcd) - meson_crtc->vsync_forced = true; - else - meson_crtc->vsync_forced = false; + if (priv->viu.osd1_afbcd) { + priv->afbcd.ops->reset(priv); + priv->afbcd.ops->setup(priv); + priv->afbcd.ops->enable(priv); + } priv->viu.osd1_commit = false; } @@ -595,15 +591,6 @@ void meson_crtc_irq(struct meson_drm *priv) priv->viu.vd1_commit = false; } - if (meson_crtc->vsync_forced && priv->viu.osd1_afbcd) { - priv->afbcd.ops->reset(priv); - priv->afbcd.ops->setup(priv); - priv->afbcd.ops->enable(priv); - } - - if (meson_crtc->vsync_disabled) - return; - drm_crtc_handle_vblank(priv->crtc); spin_lock_irqsave(&priv->drm->event_lock, flags); diff --git a/drivers/gpu/drm/meson/meson_osd_afbcd.c b/drivers/gpu/drm/meson/meson_osd_afbcd.c index aae4341bedaf..6d97bb4be3ca 100644 --- a/drivers/gpu/drm/meson/meson_osd_afbcd.c +++ b/drivers/gpu/drm/meson/meson_osd_afbcd.c @@ -12,6 +12,7 @@ #include "meson_drv.h" #include "meson_registers.h" #include "meson_viu.h" +#include "meson_rdma.h" #include "meson_osd_afbcd.h" /* @@ -270,6 +271,14 @@ static bool meson_g12a_afbcd_supported_fmt(u64 modifier, uint32_t format) static int meson_g12a_afbcd_init(struct meson_drm *priv) { + int ret; + + ret = meson_rdma_init(priv); + if (ret) + return ret; + + meson_rdma_setup(priv); + /* Handle AFBC Decoder reset manually */ writel_bits_relaxed(MALI_AFBCD_MANUAL_RESET, MALI_AFBCD_MANUAL_RESET, priv->io_base + _REG(MALI_AFBCD_TOP_CTRL)); @@ -279,27 +288,32 @@ static int meson_g12a_afbcd_init(struct meson_drm *priv) static int meson_g12a_afbcd_reset(struct meson_drm *priv) { - writel_relaxed(VIU_SW_RESET_G12A_AFBC_ARB | - VIU_SW_RESET_G12A_OSD1_AFBCD, - priv->io_base + _REG(VIU_SW_RESET)); - writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET)); + meson_rdma_stop(priv); + + meson_rdma_writel_sync(priv, VIU_SW_RESET_G12A_AFBC_ARB | + VIU_SW_RESET_G12A_OSD1_AFBCD, + VIU_SW_RESET); + meson_rdma_writel_sync(priv, 0, VIU_SW_RESET); return 0; } static int meson_g12a_afbcd_enable(struct meson_drm *priv) { - writel_relaxed(VPU_MAFBC_IRQ_SURFACES_COMPLETED | - VPU_MAFBC_IRQ_CONFIGURATION_SWAPPED | - VPU_MAFBC_IRQ_DECODE_ERROR | - VPU_MAFBC_IRQ_DETILING_ERROR, - priv->io_base + _REG(VPU_MAFBC_IRQ_MASK)); + meson_rdma_writel_sync(priv, VPU_MAFBC_IRQ_SURFACES_COMPLETED | + VPU_MAFBC_IRQ_CONFIGURATION_SWAPPED | + VPU_MAFBC_IRQ_DECODE_ERROR | + VPU_MAFBC_IRQ_DETILING_ERROR, + VPU_MAFBC_IRQ_MASK); - writel_bits_relaxed(VPU_MAFBC_S0_ENABLE, VPU_MAFBC_S0_ENABLE, - priv->io_base + _REG(VPU_MAFBC_SURFACE_CFG)); + meson_rdma_writel_sync(priv, VPU_MAFBC_S0_ENABLE, + VPU_MAFBC_SURFACE_CFG); + + meson_rdma_writel_sync(priv, VPU_MAFBC_DIRECT_SWAP, + VPU_MAFBC_COMMAND); - writel_relaxed(VPU_MAFBC_DIRECT_SWAP, - priv->io_base + _REG(VPU_MAFBC_COMMAND)); + /* This will enable the RDMA replaying the register writes on vsync */ + meson_rdma_flush(priv); return 0; } @@ -330,36 +344,36 @@ static int meson_g12a_afbcd_setup(struct meson_drm *priv) AFBC_FORMAT_MOD_BLOCK_SIZE_32x8) format |= FIELD_PREP(VPU_MAFBC_SUPER_BLOCK_ASPECT, 1); - writel_relaxed(format, - priv->io_base + _REG(VPU_MAFBC_FORMAT_SPECIFIER_S0)); - - writel_relaxed(priv->viu.osd1_addr, - priv->io_base + _REG(VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0)); - writel_relaxed(0, - priv->io_base + _REG(VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0)); - - writel_relaxed(priv->viu.osd1_width, - priv->io_base + _REG(VPU_MAFBC_BUFFER_WIDTH_S0)); - writel_relaxed(ALIGN(priv->viu.osd1_height, 32), - priv->io_base + _REG(VPU_MAFBC_BUFFER_HEIGHT_S0)); - - writel_relaxed(0, - priv->io_base + _REG(VPU_MAFBC_BOUNDING_BOX_X_START_S0)); - writel_relaxed(priv->viu.osd1_width - 1, - priv->io_base + _REG(VPU_MAFBC_BOUNDING_BOX_X_END_S0)); - writel_relaxed(0, - priv->io_base + _REG(VPU_MAFBC_BOUNDING_BOX_Y_START_S0)); - writel_relaxed(priv->viu.osd1_height - 1, - priv->io_base + _REG(VPU_MAFBC_BOUNDING_BOX_Y_END_S0)); - - writel_relaxed(MESON_G12A_AFBCD_OUT_ADDR, - priv->io_base + _REG(VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0)); - writel_relaxed(0, - priv->io_base + _REG(VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0)); - - writel_relaxed(priv->viu.osd1_width * - (meson_g12a_afbcd_bpp(priv->afbcd.format) / 8), - priv->io_base + _REG(VPU_MAFBC_OUTPUT_BUF_STRIDE_S0)); + meson_rdma_writel_sync(priv, format, + VPU_MAFBC_FORMAT_SPECIFIER_S0); + + meson_rdma_writel_sync(priv, priv->viu.osd1_addr, + VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0); + meson_rdma_writel_sync(priv, 0, + VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0); + + meson_rdma_writel_sync(priv, priv->viu.osd1_width, + VPU_MAFBC_BUFFER_WIDTH_S0); + meson_rdma_writel_sync(priv, ALIGN(priv->viu.osd1_height, 32), + VPU_MAFBC_BUFFER_HEIGHT_S0); + + meson_rdma_writel_sync(priv, 0, + VPU_MAFBC_BOUNDING_BOX_X_START_S0); + meson_rdma_writel_sync(priv, priv->viu.osd1_width - 1, + VPU_MAFBC_BOUNDING_BOX_X_END_S0); + meson_rdma_writel_sync(priv, 0, + VPU_MAFBC_BOUNDING_BOX_Y_START_S0); + meson_rdma_writel_sync(priv, priv->viu.osd1_height - 1, + VPU_MAFBC_BOUNDING_BOX_Y_END_S0); + + meson_rdma_writel_sync(priv, MESON_G12A_AFBCD_OUT_ADDR, + VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0); + meson_rdma_writel_sync(priv, 0, + VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0); + + meson_rdma_writel_sync(priv, priv->viu.osd1_width * + (meson_g12a_afbcd_bpp(priv->afbcd.format) / 8), + VPU_MAFBC_OUTPUT_BUF_STRIDE_S0); return 0; }