diff mbox series

drm/amdgpu/display: fix build error casused by CONFIG_DRM_AMD_DC_DCN2_1

Message ID 20191015165117.31195-1-hersenxs.wu@amd.com (mailing list archive)
State New, archived
Headers show
Series drm/amdgpu/display: fix build error casused by CONFIG_DRM_AMD_DC_DCN2_1 | expand

Commit Message

Wu, Hersen Oct. 15, 2019, 4:51 p.m. UTC
when CONFIG_DRM_AMD_DC_DCN2_1 is not enable in .config,
there is build error. struct dpm_clocks shoud not be
guarded.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 3 ---
 1 file changed, 3 deletions(-)

Comments

Bhawanpreet Lakha Oct. 15, 2019, 4:58 p.m. UTC | #1
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>

On 2019-10-15 12:51 p.m., Hersen Wu wrote:
> when CONFIG_DRM_AMD_DC_DCN2_1 is not enable in .config,
> there is build error. struct dpm_clocks shoud not be
> guarded.
>
> Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
> ---
>   drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 3 ---
>   1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
> index 24d65dbbd749..ef7df9ef6d7e 100644
> --- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
> +++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
> @@ -249,8 +249,6 @@ struct pp_smu_funcs_nv {
>   };
>   #endif
>   
> -#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
> -
>   #define PP_SMU_NUM_SOCCLK_DPM_LEVELS  8
>   #define PP_SMU_NUM_DCFCLK_DPM_LEVELS  8
>   #define PP_SMU_NUM_FCLK_DPM_LEVELS    4
> @@ -288,7 +286,6 @@ struct pp_smu_funcs_rn {
>   	enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
>   			struct dpm_clocks *clock_table);
>   };
> -#endif
>   
>   struct pp_smu_funcs {
>   	struct pp_smu ctx;
Liang, Prike Oct. 16, 2019, 2:09 a.m. UTC | #2
Reviewed-by: Prike Liang <Prike.Liang@amd.com>

BTW, would you help clarify why PP_SMU_NUM_DCFCLK_DPM_LEVELS is different from the smu12_driver_if.h define 
NUM_DCFCLK_DPM_LEVELS in you other patch about drm/amdgpu/powerplay: add renoir funcs to support dc.

Is there can track the macro definition update ?

Thanks,
Prike
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Hersen Wu
> Sent: Wednesday, October 16, 2019 12:51 AM
> To: dri-devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
> Cc: Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Lakha, Bhawanpreet
> <Bhawanpreet.Lakha@amd.com>; Wentland, Harry
> <Harry.Wentland@amd.com>; Wu, Hersen <hersenxs.wu@amd.com>
> Subject: [PATCH] drm/amdgpu/display: fix build error casused by
> CONFIG_DRM_AMD_DC_DCN2_1
> 
> when CONFIG_DRM_AMD_DC_DCN2_1 is not enable in .config, there is build
> error. struct dpm_clocks shoud not be guarded.
> 
> Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
> ---
>  drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
> b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
> index 24d65dbbd749..ef7df9ef6d7e 100644
> --- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
> +++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
> @@ -249,8 +249,6 @@ struct pp_smu_funcs_nv {  };  #endif
> 
> -#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
> -
>  #define PP_SMU_NUM_SOCCLK_DPM_LEVELS  8  #define
> PP_SMU_NUM_DCFCLK_DPM_LEVELS  8
>  #define PP_SMU_NUM_FCLK_DPM_LEVELS    4
> @@ -288,7 +286,6 @@ struct pp_smu_funcs_rn {
>  	enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
>  			struct dpm_clocks *clock_table);
>  };
> -#endif
> 
>  struct pp_smu_funcs {
>  	struct pp_smu ctx;
> --
> 2.17.1
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index 24d65dbbd749..ef7df9ef6d7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -249,8 +249,6 @@  struct pp_smu_funcs_nv {
 };
 #endif
 
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
-
 #define PP_SMU_NUM_SOCCLK_DPM_LEVELS  8
 #define PP_SMU_NUM_DCFCLK_DPM_LEVELS  8
 #define PP_SMU_NUM_FCLK_DPM_LEVELS    4
@@ -288,7 +286,6 @@  struct pp_smu_funcs_rn {
 	enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
 			struct dpm_clocks *clock_table);
 };
-#endif
 
 struct pp_smu_funcs {
 	struct pp_smu ctx;