From patchwork Thu Oct 17 09:48:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11195287 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8A8C8112B for ; Thu, 17 Oct 2019 09:48:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 72D122089C for ; Thu, 17 Oct 2019 09:48:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 72D122089C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 57D6A6EA36; Thu, 17 Oct 2019 09:48:36 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by gabe.freedesktop.org (Postfix) with ESMTPS id 84FF56EA36 for ; Thu, 17 Oct 2019 09:48:34 +0000 (UTC) Received: by mail-wm1-x344.google.com with SMTP id p7so1845989wmp.4 for ; Thu, 17 Oct 2019 02:48:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5iLLS7Y0EigWyUmvKnwWYMeuPvGCs9F0h7Crje9w3Z4=; b=TJEWy7cHMJYcssUqcX+8VJx7ruuqv1jsDmGdYZeSOMG6486tJiZf9umDNArq0Prlw7 Uerqo0+RHUqr0j4fqB5MYBGJFLyjQYpC0Bt0LmnwsVNStE2kg1sV+yFL9yQfINe3FmZd ayJqec3qySNcLc1hmuK1xiW+ZiCE5PjISYkq/vH/CdqLSPJuz3Ftbr/X9sUPtVmyCWGf 78Y+gb8akDA4xaGktqtUKHbqafaWBOfxriRVpHXmBFqyvIpG1VdfiugEBzD5xtCBU1kF VOQyGc5FVLQVA5THM4QFMWSIqd0iAYpUyaPPp4s4oNDYjKkTASVVHwzFKwtOj4kSJbXz j09g== X-Gm-Message-State: APjAAAWT1+k27ssDdyhrjTTrgeGx3I0gvM8n5+tAmKuROcWaVUzD4h2V kLkiHK9SwemIQmOKYK+okSBULHxr2KHeiA== X-Google-Smtp-Source: APXvYqxfe3Pk1/LziocmZDXLLEnmpKfeDMqewKinRi8tGvfp3Ku7InG32G6MDjy89H4CUUY0+HrJtQ== X-Received: by 2002:a7b:c8d9:: with SMTP id f25mr1951718wml.173.1571305712633; Thu, 17 Oct 2019 02:48:32 -0700 (PDT) Received: from localhost.localdomain (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id t83sm2764506wmt.18.2019.10.17.02.48.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 02:48:32 -0700 (PDT) From: Neil Armstrong To: dri-devel@lists.freedesktop.org Subject: [PATCH v2 2/3] drm/meson: add RDMA module driver Date: Thu, 17 Oct 2019 11:48:25 +0200 Message-Id: <20191017094826.21552-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20191017094826.21552-1-narmstrong@baylibre.com> References: <20191017094826.21552-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5iLLS7Y0EigWyUmvKnwWYMeuPvGCs9F0h7Crje9w3Z4=; b=M+29CLpvbth+qIKUr1cAPhn/E3zmxgmcySpB+nm7dDJh55N/P/kVcLzcAUhNO7kNwK 0mTWL9rbP+4u6hKspusYli3udPZ+BwAsJCpFiUH1yFfhFSFGs594RIbje/I42yZFfkii kkAU7wNDldk28IABqlHTQneVZNCfbUa1AutjYFh9Q5rpyDiI7jZ9wrkiDSBdanUll4P7 M9dBS42sEzsmU3t69DVzrJATWxqDxF+NiY5vIzwHDIwTcvl2hhe9VZnr9R+0phbVcQ/4 ad0ILvRf64ZJJ/WMhXvp3Zmsk0g6j/rD3HRO9Wcl7nk1bZ0RrBKemXo1P2odDgRL+8F4 S1xg== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khilman@baylibre.com, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The VPU embeds a "Register DMA" that can write a sequence of registers on the VPU AHB bus, either manually or triggered by an internal IRQ event like VSYNC or a line input counter. The initial implementation handles a single channel (over 8), triggered by the VSYNC irq and does not handle the RDMA irq. The RDMA will be usefull to reset and program the AFBC decoder unit on each vsync without involving the interrupt handler that can be masked for a log period of time, producing display glitches. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/Makefile | 2 +- drivers/gpu/drm/meson/meson_drv.c | 14 ++- drivers/gpu/drm/meson/meson_drv.h | 6 ++ drivers/gpu/drm/meson/meson_rdma.c | 132 +++++++++++++++++++++++++++++ drivers/gpu/drm/meson/meson_rdma.h | 21 +++++ 5 files changed, 171 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/meson/meson_rdma.c create mode 100644 drivers/gpu/drm/meson/meson_rdma.h diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile index b1fa055aaed3..9e36f0c7b816 100644 --- a/drivers/gpu/drm/meson/Makefile +++ b/drivers/gpu/drm/meson/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only meson-drm-y := meson_drv.o meson_plane.o meson_crtc.o meson_venc_cvbs.o meson-drm-y += meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o meson_overlay.o -meson-drm-y += meson_osd_afbcd.o +meson-drm-y += meson_osd_afbcd.o meson_rdma.o obj-$(CONFIG_DRM_MESON) += meson-drm.o obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c index 0f31e70bb94f..2200d8b5252e 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -33,6 +33,7 @@ #include "meson_venc_cvbs.h" #include "meson_viu.h" #include "meson_vpp.h" +#include "meson_rdma.h" #define DRIVER_NAME "meson" #define DRIVER_DESC "Amlogic Meson DRM driver" @@ -295,8 +296,11 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) meson_venc_init(priv); meson_vpp_init(priv); meson_viu_init(priv); - if (priv->afbcd.ops) - priv->afbcd.ops->init(priv); + if (priv->afbcd.ops) { + ret = priv->afbcd.ops->init(priv); + if (ret) + return ret; + } /* Encoder Initialization */ @@ -367,12 +371,16 @@ static void meson_drv_unbind(struct device *dev) meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2); } + if (priv->afbcd.ops) { + priv->afbcd.ops->reset(priv); + meson_rdma_free(priv); + } + drm_dev_unregister(drm); drm_irq_uninstall(drm); drm_kms_helper_poll_fini(drm); drm_mode_config_cleanup(drm); drm_dev_put(drm); - } static const struct component_master_ops meson_drv_master_ops = { diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h index de25349be8aa..9995d74c5ded 100644 --- a/drivers/gpu/drm/meson/meson_drv.h +++ b/drivers/gpu/drm/meson/meson_drv.h @@ -139,6 +139,12 @@ struct meson_drm { u64 modifier; u32 format; } afbcd; + + struct { + dma_addr_t addr_phys; + uint32_t *addr; + unsigned int offset; + } rdma; }; static inline int meson_vpu_is_compatible(struct meson_drm *priv, diff --git a/drivers/gpu/drm/meson/meson_rdma.c b/drivers/gpu/drm/meson/meson_rdma.c new file mode 100644 index 000000000000..4ef5e402d5ca --- /dev/null +++ b/drivers/gpu/drm/meson/meson_rdma.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 BayLibre, SAS + * Author: Neil Armstrong + */ + +#include +#include + +#include "meson_drv.h" +#include "meson_registers.h" +#include "meson_rdma.h" + +/* + * The VPU embeds a "Register DMA" that can write a sequence of registers + * on the VPU AHB bus, either manually or triggered by an internal IRQ + * event like VSYNC or a line input counter. + * The initial implementation handles a single channel (over 8), triggered + * by the VSYNC irq and does not handle the RDMA irq. + */ + +#define RDMA_DESC_SIZE (sizeof(uint32_t) * 2) + +int meson_rdma_init(struct meson_drm *priv) +{ + /* Allocate a 4k buffer */ + priv->rdma.addr = dma_alloc_coherent(priv->dev, SZ_4K, + &priv->rdma.addr_phys, + GFP_KERNEL); + if (!priv->rdma.addr) + return -ENOMEM; + + priv->rdma.offset = 0; + + writel_relaxed(RDMA_CTRL_SW_RESET, + priv->io_base + _REG(RDMA_CTRL)); + writel_relaxed(RDMA_DEFAULT_CONFIG | + FIELD_PREP(RDMA_CTRL_AHB_WR_BURST, 3) | + FIELD_PREP(RDMA_CTRL_AHB_RD_BURST, 0), + priv->io_base + _REG(RDMA_CTRL)); + + return 0; +} + +void meson_rdma_free(struct meson_drm *priv) +{ + if (!priv->rdma.addr && !priv->rdma.addr_phys) + return; + + meson_rdma_stop(priv); + + dma_free_coherent(priv->dev, SZ_4K, + priv->rdma.addr, priv->rdma.addr_phys); + + priv->rdma.addr = NULL; + priv->rdma.addr_phys = (dma_addr_t)NULL; +} + +void meson_rdma_setup(struct meson_drm *priv) +{ + /* Channel 1: Write Flag, No Address Increment */ + writel_bits_relaxed(RDMA_ACCESS_RW_FLAG_CHAN1 | + RDMA_ACCESS_ADDR_INC_CHAN1, + RDMA_ACCESS_RW_FLAG_CHAN1, + priv->io_base + _REG(RDMA_ACCESS_AUTO)); +} + +void meson_rdma_stop(struct meson_drm *priv) +{ + writel_bits_relaxed(RDMA_IRQ_CLEAR_CHAN1, + RDMA_IRQ_CLEAR_CHAN1, + priv->io_base + _REG(RDMA_CTRL)); + + /* Stop Channel 1 */ + writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1, + FIELD_PREP(RDMA_ACCESS_ADDR_INC_CHAN1, + RDMA_ACCESS_TRIGGER_STOP), + priv->io_base + _REG(RDMA_ACCESS_AUTO)); +} + +void meson_rdma_reset(struct meson_drm *priv) +{ + meson_rdma_stop(priv); + + priv->rdma.offset = 0; +} + +static void meson_rdma_writel(struct meson_drm *priv, uint32_t val, + uint32_t reg) +{ + if (priv->rdma.offset >= (SZ_4K / RDMA_DESC_SIZE)) { + dev_warn_once(priv->dev, "%s: overflow\n", __func__); + return; + } + + priv->rdma.addr[priv->rdma.offset++] = reg; + priv->rdma.addr[priv->rdma.offset++] = val; +} + +/* + * This will add the register to the RDMA buffer and write it to the + * hardware at the same time. + * When meson_rdma_flush is called, the RDMA will replay the register + * writes in order. + */ +void meson_rdma_writel_sync(struct meson_drm *priv, uint32_t val, uint32_t reg) +{ + meson_rdma_writel(priv, val, reg); + + writel_relaxed(val, priv->io_base + _REG(reg)); +} + +void meson_rdma_flush(struct meson_drm *priv) +{ + meson_rdma_stop(priv); + + /* Start of Channel 1 register writes buffer */ + writel(priv->rdma.addr_phys, + priv->io_base + _REG(RDMA_AHB_START_ADDR_1)); + + /* Last byte on Channel 1 register writes buffer */ + writel(priv->rdma.addr_phys + (priv->rdma.offset * RDMA_DESC_SIZE) - 1, + priv->io_base + _REG(RDMA_AHB_END_ADDR_1)); + + /* Trigger Channel 1 on VSYNC event */ + writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1, + FIELD_PREP(RDMA_ACCESS_TRIGGER_CHAN1, + RDMA_ACCESS_TRIGGER_VSYNC), + priv->io_base + _REG(RDMA_ACCESS_AUTO)); + + priv->rdma.offset = 0; +} diff --git a/drivers/gpu/drm/meson/meson_rdma.h b/drivers/gpu/drm/meson/meson_rdma.h new file mode 100644 index 000000000000..3870bff7b47f --- /dev/null +++ b/drivers/gpu/drm/meson/meson_rdma.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __MESON_RDMA_H +#define __MESON_RDMA_H + +#include "meson_drv.h" + +int meson_rdma_init(struct meson_drm *priv); +void meson_rdma_free(struct meson_drm *priv); +void meson_rdma_setup(struct meson_drm *priv); +void meson_rdma_reset(struct meson_drm *priv); +void meson_rdma_stop(struct meson_drm *priv); + +void meson_rdma_writel_sync(struct meson_drm *priv, uint32_t val, uint32_t reg); +void meson_rdma_flush(struct meson_drm *priv); + +#endif /* __MESON_RDMA_H */