From patchwork Sat Nov 23 05:29:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Anderson X-Patchwork-Id: 11259951 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 407E26C1 for ; Mon, 25 Nov 2019 08:07:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 298FC20815 for ; Mon, 25 Nov 2019 08:07:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 298FC20815 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E137B89548; Mon, 25 Nov 2019 08:07:42 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pj1-x104a.google.com (mail-pj1-x104a.google.com [IPv6:2607:f8b0:4864:20::104a]) by gabe.freedesktop.org (Postfix) with ESMTPS id 115336F5A6 for ; Sat, 23 Nov 2019 05:29:05 +0000 (UTC) Received: by mail-pj1-x104a.google.com with SMTP id t7so4025636pjg.12 for ; Fri, 22 Nov 2019 21:29:05 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=bVyv4YX7sBcmbg/cjO2xV4ng37xlI4Fx14aOVCg/YPk=; b=NJAXeJPvup9VNWX7cvAX8aX134c2UAz71ThswDoHspX8jgMfY1SF9oTcX4tChUc/HK J7UcoQ3y3mDjCqpQ0pi3FFCBlopgneOnW/+ANe7qY77ROW0NUGb5ckXol/BL5HevR3+c mERV4rrv3M5ZXQlqnXyp3qvx9zuP6BG8JnSAxop1UfjVFjRNWldABP/x3FxzWjhBHRd8 vBuChdqXuWDOSeXMzyiNN1Y8T3K+W/IhW3Sm2hX782osY3CtfXAuZPtx/2QOF6+aRJij sWgJR1tt919hPqiPEJjDzosk8oum0dhCEqBrtB2cKQeeSxMs4rCRNkX9ORnncCEMysDe gi6g== X-Gm-Message-State: APjAAAXnegtHn51uQVLBK2DPsrVY7hWbig9frLm7EbSSsi6Nqxdu1xDI nNOIk9SGiohH+rUtpIYotSIFtwd3wBQudk8BAEU5fQ== X-Google-Smtp-Source: APXvYqxjRM9ai1CA9dNK82G+vFlip7YVCLCIXbLIH1Csg4LCLSDnDb0tkEU778iwITRS6ZGh5nPtALd01sCBSgOx+P7pbA== X-Received: by 2002:a63:368c:: with SMTP id d134mr19610973pga.321.1574486944440; Fri, 22 Nov 2019 21:29:04 -0800 (PST) Date: Fri, 22 Nov 2019 21:29:00 -0800 Message-Id: <20191123052900.77205-1-thomasanderson@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog Subject: [PATCH] drm/amd/display: Reduce HDMI pixel encoding if max clock is exceeded From: Thomas Anderson To: Harry Wentland , Leo Li , Alex Deucher X-Mailman-Approved-At: Mon, 25 Nov 2019 08:07:41 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:message-id:mime-version:subject:from:to:cc; bh=bVyv4YX7sBcmbg/cjO2xV4ng37xlI4Fx14aOVCg/YPk=; b=IPue6pH+iGFcyTATyXECvU11P2erhBngc5DZDw11DE48T3vmrNrq3F/wuawLSgPQS8 uAeMHCTJgtnFhivGAdK4UJdOvjZSSSqf8AUr5PEJVudhYEHTdTOtwzFL20vc96kkNn+X 3DUz6HFHP+idBPxiFTl9yALA7j71nWC8lCZJPo65yjXErrbFZjlZA+30+pimC9oFmjRR IG2ISB2Ah3gctyeBATexyLgYHYVnYW1euFzZLOT10vAogI0L8dTou99IJtiIpQmalROi kuVR4o/5csF44JRTjcb+pBKbrh96WXRg04ta3T99TBtzrOfzhV1rnLnbKIR8FIeoTHBB BozA== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Anderson , David Airlie , David Francis , linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, Nicholas Kazlauskas , dri-devel@lists.freedesktop.org, =?utf-8?q?Christian_K=C3=B6nig?= Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" For high-res (8K) or HFR (4K120) displays, using uncompressed pixel formats like YCbCr444 would exceed the bandwidth of HDMI 2.0, so the "interesting" modes would be disabled, leaving only low-res or low framerate modes. This change lowers the pixel encoding to 4:2:2 or 4:2:0 if the max TMDS clock is exceeded. Verified that 8K30 and 4K120 are now available and working with a Samsung Q900R over an HDMI 2.0b link from a Radeon 5700. Signed-off-by: Thomas Anderson --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 ++++++++++++++----- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4139f129eafb..a507a6f04c82 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3269,13 +3269,15 @@ static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out) timing_out->display_color_depth--; } -static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out, - const struct drm_display_info *info) +static void adjust_timing_from_display_info( + struct dc_crtc_timing *timing_out, + const struct drm_display_info *info, + const struct drm_display_mode *mode_in) { int normalized_clk; - if (timing_out->display_color_depth <= COLOR_DEPTH_888) + if (timing_out->display_color_depth < COLOR_DEPTH_888) return; - do { + while (timing_out->display_color_depth > COLOR_DEPTH_888) { normalized_clk = timing_out->pix_clk_100hz / 10; /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) @@ -3297,9 +3299,23 @@ static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_ if (normalized_clk <= info->max_tmds_clock) return; reduce_mode_colour_depth(timing_out); + } - } while (timing_out->display_color_depth > COLOR_DEPTH_888); - + /* The color depth is 888 and cannot be reduced any further, but the + * clock would still exceed the max tmds clock. Try reducing the pixel + * encoding next. + */ + if (timing_out->pixel_encoding == PIXEL_ENCODING_RGB || + timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR444) { + /* YCBCR422 is always supported. */ + timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR422; + normalized_clk = (timing_out->pix_clk_100hz * 3) / 40; + if (normalized_clk <= info->max_tmds_clock) + return; + } + /* YCBCR420 may only be supported on specific modes. */ + if (drm_mode_is_420_also(info, mode_in)) + timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; } static void fill_stream_properties_from_drm_display_mode( @@ -3366,7 +3382,7 @@ static void fill_stream_properties_from_drm_display_mode( stream->out_transfer_func->type = TF_TYPE_PREDEFINED; stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) - adjust_colour_depth_from_display_info(timing_out, info); + adjust_timing_from_display_info(timing_out, info, mode_in); } static void fill_audio_info(struct audio_info *audio_info,