From patchwork Thu Dec 5 09:27:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 11274427 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F36A8112B for ; Thu, 5 Dec 2019 09:28:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DBA1024651 for ; Thu, 5 Dec 2019 09:28:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DBA1024651 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 216D66E048; Thu, 5 Dec 2019 09:27:58 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTP id 04D5D6F610 for ; Thu, 5 Dec 2019 09:27:55 +0000 (UTC) X-UUID: 4397a3792bb24f289cc44234b3e2602b-20191205 X-UUID: 4397a3792bb24f289cc44234b3e2602b-20191205 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 896328631; Thu, 05 Dec 2019 17:27:52 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 5 Dec 2019 17:27:35 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 5 Dec 2019 17:26:53 +0800 From: Bibby Hsieh To: David Airlie , Matthias Brugger , Daniel Vetter , , Subject: [PATCH v4 7/7] drm/mediatek: apply CMDQ control flow Date: Thu, 5 Dec 2019 17:27:49 +0800 Message-ID: <20191205092749.4021-8-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20191205092749.4021-1-bibby.hsieh@mediatek.com> References: <20191205092749.4021-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=uM1ke7og2J6EZV2kT8QK5FY4tjoIYTgjFwSyXoj2uGo=; b=Qo6VPVEoRw1h3RBGC6Nn1jCHRNzGuklITxKfH4XTP33koBDQnt17gM6FgBPdoMH8+Hk9CCYhkZGtC7wwzF6yiqwzIiyzaQdwndErC4UJCoBXZK0NMsBk6iHXPkDM+DrIkSG4KkWIpZFDTL0+5TxLLZE6GDEhec/fAX+M/Sm85FA=; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drinkcat@chromium.org, srv_heupstream@mediatek.com, Yongqiang Niu , linux-kernel@vger.kernel.org, tfiga@chromium.org, Thierry Reding , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Unlike other SoCs, MT8183 does not have "shadow" registers for performaing an atomic video mode set or page flip at vblank/vsync. The CMDQ (Commend Queue) in MT8183 is used to help update all relevant display controller registers with critical time limation. Signed-off-by: YT Shen Signed-off-by: CK Hu Signed-off-by: Philipp Zabel Signed-off-by: Bibby Hsieh Signed-off-by: Yongqiang Niu Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 56 +++++++++++++++++++++---- 1 file changed, 49 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 8c6231ed6f55..496dffe962af 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include "mtk_drm_drv.h" #include "mtk_drm_crtc.h" @@ -43,6 +45,9 @@ struct mtk_drm_crtc { bool pending_planes; bool pending_async_planes; + struct cmdq_client *cmdq_client; + u32 cmdq_event; + void __iomem *config_regs; const struct mtk_mmsys_reg_data *mmsys_reg_data; struct mtk_disp_mutex *mutex; @@ -234,6 +239,13 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, return NULL; } +#ifdef CONFIG_MTK_CMDQ +static void ddp_cmdq_cb(struct cmdq_cb_data data) +{ + cmdq_pkt_destroy(data.data); +} +#endif + static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) { struct drm_crtc *crtc = &mtk_crtc->base; @@ -378,7 +390,8 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) } } -static void mtk_crtc_ddp_config(struct drm_crtc *crtc) +static void mtk_crtc_ddp_config(struct drm_crtc *crtc, + struct cmdq_pkt *cmdq_handle) { struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); @@ -394,7 +407,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) if (state->pending_config) { mtk_ddp_comp_config(comp, state->pending_width, state->pending_height, - state->pending_vrefresh, 0, NULL); + state->pending_vrefresh, 0, + cmdq_handle); state->pending_config = false; } @@ -414,7 +428,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) if (comp) mtk_ddp_comp_layer_config(comp, local_layer, - plane_state, NULL); + plane_state, + cmdq_handle); plane_state->pending.config = false; } mtk_crtc->pending_planes = false; @@ -435,7 +450,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) if (comp) mtk_ddp_comp_layer_config(comp, local_layer, - plane_state, NULL); + plane_state, + cmdq_handle); plane_state->pending.async_config = false; } mtk_crtc->pending_async_planes = false; @@ -444,6 +460,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) { + struct cmdq_pkt *cmdq_handle; struct drm_crtc *crtc = &mtk_crtc->base; struct mtk_drm_private *priv = crtc->dev->dev_private; unsigned int pending_planes = 0, pending_async_planes = 0; @@ -472,9 +489,18 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) if (priv->data->shadow_register) { mtk_disp_mutex_acquire(mtk_crtc->mutex); - mtk_crtc_ddp_config(crtc); + mtk_crtc_ddp_config(crtc, NULL); mtk_disp_mutex_release(mtk_crtc->mutex); } +#ifdef CONFIG_MTK_CMDQ + if (mtk_crtc->cmdq_client) { + cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); + cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); + cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event); + mtk_crtc_ddp_config(crtc, cmdq_handle); + cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); + } +#endif mutex_unlock(&mtk_crtc->hw_lock); } @@ -643,8 +669,8 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); struct mtk_drm_private *priv = crtc->dev->dev_private; - if (!priv->data->shadow_register) - mtk_crtc_ddp_config(crtc); + if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) + mtk_crtc_ddp_config(crtc, NULL); mtk_drm_finish_page_flip(mtk_crtc); } @@ -787,5 +813,21 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, priv->num_pipes++; mutex_init(&mtk_crtc->hw_lock); +#ifdef CONFIG_MTK_CMDQ + mtk_crtc->cmdq_client = + cmdq_mbox_create(dev, drm_crtc_index(&mtk_crtc->base), + 2000); + if (IS_ERR(mtk_crtc->cmdq_client)) { + dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", + drm_crtc_index(&mtk_crtc->base)); + mtk_crtc->cmdq_client = NULL; + } + ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events", + drm_crtc_index(&mtk_crtc->base), + &mtk_crtc->cmdq_event); + if (ret) + dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", + drm_crtc_index(&mtk_crtc->base)); +#endif return 0; }