Message ID | 20191213200854.31545-10-mikita.lipski@amd.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Fri, 13 Dec 2019 20:09:02 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB02.amd.com (10.181.40.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Fri, 13 Dec 2019 14:09:02 -0600 Received: from SATLEXMB02.amd.com (10.181.40.143) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Fri, 13 Dec 2019 14:09:01 -0600 Received: from mlipski-pc.amd.com (10.180.168.240) by SATLEXMB02.amd.com (10.181.40.143) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Fri, 13 Dec 2019 14:09:01 -0600 From: <mikita.lipski@amd.com> To: <amd-gfx@lists.freedesktop.org> Subject: [PATCH v9 09/18] drm/amd/display: Write DSC enable to MST DPCD Date: Fri, 13 Dec 2019 15:08:45 -0500 Message-ID: <20191213200854.31545-10-mikita.lipski@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191213200854.31545-1-mikita.lipski@amd.com> References: <20191213200854.31545-1-mikita.lipski@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Series |
DSC MST support for DRM and AMDGPU
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expand
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diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 66f266a5e10b..069b7a6f5597 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -37,6 +37,7 @@ #include "dc.h" #include "amdgpu_dm.h" #include "amdgpu_dm_irq.h" +#include "amdgpu_dm_mst_types.h" #include "dm_helpers.h" @@ -516,8 +517,24 @@ bool dm_helpers_dp_write_dsc_enable( ) { uint8_t enable_dsc = enable ? 1 : 0; + struct amdgpu_dm_connector *aconnector; + + if (!stream) + return false; + + if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { + aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; + + if (!aconnector->dsc_aux) + return false; + + return (drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1) >= 0); + } + + if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT) + return dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); - return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1); + return false; } bool dm_helpers_is_dp_sink_present(struct dc_link *link)