From patchwork Wed Dec 18 00:47:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11299187 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D43EC13B6 for ; Wed, 18 Dec 2019 00:48:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B155621835 for ; Wed, 18 Dec 2019 00:48:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Z/kLD0eo" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B155621835 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4CDBC6E1E8; Wed, 18 Dec 2019 00:48:39 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pj1-x1043.google.com (mail-pj1-x1043.google.com [IPv6:2607:f8b0:4864:20::1043]) by gabe.freedesktop.org (Postfix) with ESMTPS id A80FF6E1E8 for ; Wed, 18 Dec 2019 00:48:32 +0000 (UTC) Received: by mail-pj1-x1043.google.com with SMTP id ep17so43311pjb.4 for ; Tue, 17 Dec 2019 16:48:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5I5RsOjGn6AIw10awvPPmKNOIBhCgMn63qgGQLogkT0=; b=Z/kLD0eoZedWUdTEDSVJ6kbPawHJOoiVPCNRGbgQQgKOAw7fzhYDSK3K02mAbNdlQq Fr0oNSrqzR9oqMNnsCr8ULdLH02KZAFfz2cypDlJkWrPbgZ+koWO0EFsgvgaya0R9qXw ZlvpV3CLhTTS4eAvXf4/9iFbM0UzmmsU5A7t0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5I5RsOjGn6AIw10awvPPmKNOIBhCgMn63qgGQLogkT0=; b=AvPCZYSWCnt0GDx3ix+iXBgDB+CS+QfJU8SNCvkLgzUh8RnK8p9Hv+3Bju3nGmHYSj wy/1wKxmPXHXNZEyIT3sr/9yNveq9BfOX0NyG5xGo/53GE0ryshI89X/2DRpJ6VZyzW0 gImLgWN5eIuf9RUcU0e5ehcSHvVJMCdvl91na0EopDT4Y/zxMkGOrJJUGU0tzgf3bAV6 xYDSfR03Ba7ou7bUm0437XjXyy79mRgwKztkTUuy9wetzx71ACFilPAiaXV/o7t2QNao c2N1/RgPbrgmQO8rMfVecWup1T2ULnnqs/wwbnpKfIQx+9JCqAv1oFM9mqddcu2YlXos 9veQ== X-Gm-Message-State: APjAAAWCwU/J562v1J3aVaWxCAUfbLazD5zi9LXOAQLP0ZH3nGvqlSOz 4DemeSsqB9aK+CM2XOz47p6rcw== X-Google-Smtp-Source: APXvYqzlYuY6Q06NylLwmoyVjvz5Q+yRFHQQVef1ISO7bP+Gy7Ho4kEkiZtVedpDN3oy9tmnzGorAg== X-Received: by 2002:a17:902:9302:: with SMTP id bc2mr1101734plb.148.1576630112269; Tue, 17 Dec 2019 16:48:32 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id v72sm139885pjb.25.2019.12.17.16.48.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2019 16:48:31 -0800 (PST) From: Douglas Anderson To: Andrzej Hajda , Neil Armstrong Subject: [PATCH v2 5/9] drm/bridge: ti-sn65dsi86: Read num lanes from the DP sink Date: Tue, 17 Dec 2019 16:47:37 -0800 Message-Id: <20191217164702.v2.5.Idbd0051d0de53f7e9d18a291ea33011c0854fcc6@changeid> X-Mailer: git-send-email 2.24.1.735.g03f4e72817-goog In-Reply-To: <20191218004741.102067-1-dianders@chromium.org> References: <20191218004741.102067-1-dianders@chromium.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robdclark@chromium.org, Jernej Skrabec , Jeffrey Hugo , David Airlie , linux-arm-msm@vger.kernel.org, Jonas Karlman , Douglas Anderson , dri-devel@lists.freedesktop.org, bjorn.andersson@linaro.org, seanpaul@chromium.org, Laurent Pinchart , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" At least one panel hooked up to the bridge (AUO B116XAK01) only supports 1 lane of DP. Let's read this information and stop hardcoding 4 DP lanes. Signed-off-by: Douglas Anderson Tested-by: Rob Clark Reviewed-by: Rob Clark --- Changes in v2: None drivers/gpu/drm/bridge/ti-sn65dsi86.c | 32 +++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index d55d19759796..0fc9e97b2d98 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -313,8 +313,7 @@ static int ti_sn_bridge_attach(struct drm_bridge *bridge) goto err_dsi_host; } - /* TODO: setting to 4 lanes always for now */ - pdata->dp_lanes = 4; + /* TODO: setting to 4 MIPI lanes always for now */ dsi->lanes = 4; dsi->format = MIPI_DSI_FMT_RGB888; dsi->mode_flags = MIPI_DSI_MODE_VIDEO; @@ -511,12 +510,41 @@ static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata) usleep_range(10000, 10500); /* 10ms delay recommended by spec */ } +static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata) +{ + u8 data; + int ret; + + ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); + if (ret != 1) { + DRM_DEV_ERROR(pdata->dev, + "Can't read lane count (%d); assuming 4\n", ret); + return 4; + } + + return data & DP_LANE_COUNT_MASK; +} + static void ti_sn_bridge_enable(struct drm_bridge *bridge) { struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); unsigned int val; int ret; + /* + * Run with the maximum number of lanes that the DP sink supports. + * + * Depending use cases, we might want to revisit this later because: + * - It's plausible that someone may have run fewer lines to the + * sink than the sink actually supports, assuming that the lines + * will just be driven at a higher rate. + * - The DP spec seems to indicate that it's more important to minimize + * the number of lanes than the link rate. + * + * If we do revisit, it would be important to measure the power impact. + */ + pdata->dp_lanes = ti_sn_get_max_lanes(pdata); + /* DSI_A lane config */ val = CHA_DSI_LANES(4 - pdata->dsi->lanes); regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,