| Message ID | 20200306124930.20978-4-laurentiu.palcu@oss.nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for iMX8MQ Display Controller Subsystem | expand |
On Fri, Mar 6, 2020 at 6:50 AM Laurentiu Palcu <laurentiu.palcu@oss.nxp.com> wrote: > > From: Laurentiu Palcu <laurentiu.palcu@nxp.com> Please send to DT list if you want timely (by some definition) feedback. > Add bindings for iMX8MQ Display Controller Subsystem. > > Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com> > --- > .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml > > diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml > new file mode 100644 > index 000000000000..fde6ec8cb0c3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml > @@ -0,0 +1,85 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright 2019 NXP > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: iMX8MQ Display Controller Subsystem (DCSS) > + > +maintainers: > + - Laurentiu Palcu <laurentiu.palcu@nxp.com> > + > +description: > + > + The DCSS (display controller sub system) is used to source up to three > + display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP > + 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10 > + image processing capabilities are included to provide a solution capable of > + driving next generation high dynamic range displays. > + > +properties: > + compatible: > + const: nxp,imx8mq-dcss > + > + reg: > + maxItems: 2 Need to say what each entry is. > + > + interrupts: > + maxItems: 3 Can drop. Implied by 'items' list. > + items: > + - description: Context loader completion and error interrupt > + - description: DTG interrupt used to signal context loader trigger time > + - description: DTG interrupt for Vblank > + > + interrupt-names: > + maxItems: 3 Can drop. > + items: > + - const: ctxld > + - const: ctxld_kick > + - const: vblank > + > + clocks: > + maxItems: 5 Can drop. > + items: > + - description: Display APB clock for all peripheral PIO access interfaces > + - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL > + - description: RTRAM clock > + - description: Pixel clock, can be driver either by HDMI phy clock or MIPI > + - description: DTRC clock, needed by video decompressor > + > + clock-names: > + items: > + - const: apb > + - const: axi > + - const: rtrm > + - const: pix > + - const: dtrc > + > + port: > + type: object > + description: > + A port node pointing to the input port of a HDMI/DP or MIPI display bridge. > + > +examples: > + - | > + dcss: display-controller@32e00000 { > + compatible = "nxp,imx8mq-dcss"; > + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; > + interrupts = <6>, <8>, <9>; > + interrupt-names = "ctxld", "ctxld_kick", "vblank"; > + interrupt-parent = <&irqsteer>; > + clocks = <&clk 248>, <&clk 247>, <&clk 249>, > + <&clk 254>,<&clk 122>; > + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; > + assigned-clocks = <&clk 107>, <&clk 109>, <&clk 266>; > + assigned-clock-parents = <&clk 78>, <&clk 78>, <&clk 3>; > + assigned-clock-rates = <800000000>, > + <400000000>; > + port { > + dcss_out: endpoint { > + remote-endpoint = <&hdmi_in>; > + }; > + }; > + }; > + > -- > 2.17.1 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml new file mode 100644 index 000000000000..fde6ec8cb0c3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 NXP +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: iMX8MQ Display Controller Subsystem (DCSS) + +maintainers: + - Laurentiu Palcu <laurentiu.palcu@nxp.com> + +description: + + The DCSS (display controller sub system) is used to source up to three + display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP + 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10 + image processing capabilities are included to provide a solution capable of + driving next generation high dynamic range displays. + +properties: + compatible: + const: nxp,imx8mq-dcss + + reg: + maxItems: 2 + + interrupts: + maxItems: 3 + items: + - description: Context loader completion and error interrupt + - description: DTG interrupt used to signal context loader trigger time + - description: DTG interrupt for Vblank + + interrupt-names: + maxItems: 3 + items: + - const: ctxld + - const: ctxld_kick + - const: vblank + + clocks: + maxItems: 5 + items: + - description: Display APB clock for all peripheral PIO access interfaces + - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL + - description: RTRAM clock + - description: Pixel clock, can be driver either by HDMI phy clock or MIPI + - description: DTRC clock, needed by video decompressor + + clock-names: + items: + - const: apb + - const: axi + - const: rtrm + - const: pix + - const: dtrc + + port: + type: object + description: + A port node pointing to the input port of a HDMI/DP or MIPI display bridge. + +examples: + - | + dcss: display-controller@32e00000 { + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; + interrupts = <6>, <8>, <9>; + interrupt-names = "ctxld", "ctxld_kick", "vblank"; + interrupt-parent = <&irqsteer>; + clocks = <&clk 248>, <&clk 247>, <&clk 249>, + <&clk 254>,<&clk 122>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + assigned-clocks = <&clk 107>, <&clk 109>, <&clk 266>; + assigned-clock-parents = <&clk 78>, <&clk 78>, <&clk 3>; + assigned-clock-rates = <800000000>, + <400000000>; + port { + dcss_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; +