[v11,5/5] arm64: dts: zynqmp: zcu106-revA: Wire up the DisplayPort subsystem

Commit Message

Laurent Pinchart March 18, 2020, 3:37 p.m. UTC

Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
the DisplayPort connector.

Signed-off-by: Laurent Pinchart <[e-mail]>
---
 .../boot/dts/xilinx/zynqmp-zcu106-revA.dts    | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)

Patch

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
index 6e9efe233838..2fc6342eb05e 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -13,6 +13,7 @@ 
 #include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
 	model = "ZynqMP ZCU106 RevA";
@@ -39,6 +40,17 @@  memory@0 {
 		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
 	};
 
+	/*
+	* This clock is actually produced by the SI5341 (U69), but declaring it
+	* will result in the PS_REF_CLK being disabled at end of boot as it is
+	* unused.
+	*/
+	gtr_ref_clk_dp: clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <27000000>;
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
@@ -142,6 +154,17 @@  &dcc {
 	status = "okay";
 };
 
+&dpdma {
+	status = "okay";
+};
+
+&dpsub {
+	status = "okay";
+	phy-names = "dp-phy0", "dp-phy1";
+	phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
+	       <&psgtr 0 PHY_TYPE_DP 1 3>;
+};
+
 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
 &fpd_dma_chan1 {
 	status = "okay";
@@ -591,6 +614,12 @@  i2c@7 {
 	};
 };
 
+&psgtr {
+	status = "okay";
+	clocks = <&gtr_ref_clk_dp>;
+	clock-names = "ref3";
+};
+
 &rtc {
 	status = "okay";
 };