From patchwork Tue Jun 16 14:26:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Zimmermann X-Patchwork-Id: 11607861 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 74C291392 for ; Tue, 16 Jun 2020 14:26:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D5F720786 for ; Tue, 16 Jun 2020 14:26:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5D5F720786 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ED83B6E8D5; Tue, 16 Jun 2020 14:26:47 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mx2.suse.de (mx2.suse.de [195.135.220.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id DADFC6E8D5 for ; Tue, 16 Jun 2020 14:26:46 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 5F062ABE4; Tue, 16 Jun 2020 14:26:49 +0000 (UTC) From: Thomas Zimmermann To: airlied@redhat.com, daniel@ffwll.ch, emil.velikov@collabora.com, sam@ravnborg.org, kraxel@redhat.com, rong.a.chen@intel.com Subject: [PATCH] drm/mgag200: Don't set in MISC Date: Tue, 16 Jun 2020 16:26:30 +0200 Message-Id: <20200616142630.20129-1-tzimmermann@suse.de> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Donnelly , Daniel Vetter , Emil Velikov , =?utf-8?q?Jos=C3=A9_Roberto_de_Sou?= =?utf-8?q?za?= , Andrzej Pietrasiewicz , dri-devel@lists.freedesktop.org, Thomas Zimmermann Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The original modesetting code set MISC to 0x2d, which is , and With the conversion to atomic modesetting, accidentally got enabled as well. Revert this change and initialize MISC with a constant value of and . The bits are set in mga_crtc_set_plls(), sync flags are set in mgag200_set_mode_regs(). While at it, also rename the flag constant to match the nameing in the MGA Programming Manual. Signed-off-by: Thomas Zimmermann Reported-by: kernel test robot Suggested-by: Emil Velikov Fixes: db05f8d3dc87 ("drm/mgag200: Split MISC register update into PLL selection, SYNC and I/O") Cc: Thomas Zimmermann Cc: Sam Ravnborg Cc: Emil Velikov Cc: Dave Airlie Cc: Daniel Vetter Cc: Gerd Hoffmann Cc: "José Roberto de Souza" Cc: Andrzej Pietrasiewicz Cc: Rong Chen Cc: John Donnelly --- drivers/gpu/drm/mgag200/mgag200_mode.c | 6 ++---- drivers/gpu/drm/mgag200/mgag200_reg.h | 2 +- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c index f16bd278ab7e4..3b7235bd0bcba 100644 --- a/drivers/gpu/drm/mgag200/mgag200_mode.c +++ b/drivers/gpu/drm/mgag200/mgag200_mode.c @@ -1018,10 +1018,8 @@ static void mgag200_init_regs(struct mga_device *mdev) if (mdev->type == G200_EW3) WREG_ECRT(0x34, 0x5); - misc = RREG8(MGA_MISC_IN); - misc |= MGAREG_MISC_IOADSEL | - MGAREG_MISC_RAMMAPEN | - MGAREG_MISC_HIGH_PG_SEL; + misc = MGAREG_MISC_HPGODDEV | + MGAREG_MISC_IOADSEL; WREG8(MGA_MISC_OUT, misc); } diff --git a/drivers/gpu/drm/mgag200/mgag200_reg.h b/drivers/gpu/drm/mgag200/mgag200_reg.h index 29f7194faadc0..f6629e0d4bdf2 100644 --- a/drivers/gpu/drm/mgag200/mgag200_reg.h +++ b/drivers/gpu/drm/mgag200/mgag200_reg.h @@ -228,7 +228,7 @@ #define MGAREG_MISC_CLK_SEL_MGA_PIX (0x2 << 2) #define MGAREG_MISC_CLK_SEL_MGA_MSK (0x3 << 2) #define MGAREG_MISC_VIDEO_DIS (0x1 << 4) -#define MGAREG_MISC_HIGH_PG_SEL (0x1 << 5) +#define MGAREG_MISC_HPGODDEV BIT(5) #define MGAREG_MISC_HSYNCPOL BIT(6) #define MGAREG_MISC_VSYNCPOL BIT(7)