From patchwork Fri Jun 19 21:23:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Modem, Bhanuprakash" X-Patchwork-Id: 11614243 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1DF1C90 for ; Fri, 19 Jun 2020 13:27:58 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 06E6420DD4 for ; Fri, 19 Jun 2020 13:27:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 06E6420DD4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1FC0A6ECB8; Fri, 19 Jun 2020 13:27:54 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id C6CA66ECB4; Fri, 19 Jun 2020 13:27:49 +0000 (UTC) IronPort-SDR: iopnGM7jPBLpyTc/3LLLJ4BIyyvDaRigkbGx2/I/4aexohlIJDiwiRQ2wq2A5Pd54tv+gdKyDL 6qISjrLU3dhg== X-IronPort-AV: E=McAfee;i="6000,8403,9656"; a="208188889" X-IronPort-AV: E=Sophos;i="5.75,255,1589266800"; d="scan'208";a="208188889" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jun 2020 06:27:49 -0700 IronPort-SDR: L78Qz8sH+qjrsAReprFAkkkcVdqcgsgUk0PWlbigH7Y0gbWn0944aI7LHi0YLqH8BL7b5kBXDq iVL69QpU+4lA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,255,1589266800"; d="scan'208";a="421849374" Received: from bhanu-nuc8i7beh.iind.intel.com ([10.145.162.210]) by orsmga004.jf.intel.com with ESMTP; 19 Jun 2020 06:27:47 -0700 From: Bhanuprakash Modem To: bhanuprakash.modem@intel.com, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [v6 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD Date: Sat, 20 Jun 2020 02:53:54 +0530 Message-Id: <20200619212356.19285-2-bhanuprakash.modem@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200619212356.19285-1-bhanuprakash.modem@intel.com> References: <20200619212356.19285-1-bhanuprakash.modem@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Manasi Navare DP sink device sets the Ignore MSA bit in its DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to ignore the MSA video timing parameters and its ability to support seamless video timing change over a range of timing exposed by DisplayID and EDID. This is required for the sink to indicate that it is Adaptive sync capable. v3: * Fi the typo in commit message (Manasi) v2: * Rename to describe what the function does (Jani Nikula) Cc: Jani Nikula Cc: Ville Syrjälä Cc: Harry Wentland Cc: Nicholas Kazlauskas Signed-off-by: Manasi Navare Reviewed-by: Harry Wentland --- include/drm/drm_dp_helper.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1165ec105638..e47dc22ebf50 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1457,6 +1457,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) DP_ALTERNATE_SCRAMBLER_RESET_CAP; } +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ +static inline bool +drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DOWN_STREAM_PORT_COUNT] & + DP_MSA_TIMING_PAR_IGNORED; +} + /* * DisplayPort AUX channel */