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[83.6.167.207]) by smtp.googlemail.com with ESMTPSA id d23sm4696253ejj.74.2020.07.26.04.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Jul 2020 04:14:45 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Subject: [PATCH 8/9] clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk Date: Sun, 26 Jul 2020 13:12:05 +0200 Message-Id: <20200726111215.22361-9-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200726111215.22361-1-konradybcio@gmail.com> References: <20200726111215.22361-1-konradybcio@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Sun, 26 Jul 2020 15:02:45 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof Wilczynski , Jeffrey Hugo , David Airlie , Michael Turquette , dri-devel@lists.freedesktop.org, Bjorn Andersson , AngeloGioacchino Del Regno , Sam Ravnborg , linux-clk@vger.kernel.org, Kishon Vijay Abraham I , martin.botka1@gmail.com, Andy Gross , Brian Masney , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Xiaozhe Shi , Rob Herring , Sean Paul , Ben Dooks , Felipe Balbi , Stephen Boyd , Greg Kroah-Hartman , linux-usb@vger.kernel.org, Harigovindan P , linux-kernel@vger.kernel.org, zhengbin , Manu Gautam , Vinod Koul , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add missing halt_check, hwcg_reg and hwcg_bit properties. These were likely omitted when porting the driver upstream. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sdm660.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c index a85283786278..f0b47b7d50ca 100644 --- a/drivers/clk/qcom/gcc-sdm660.c +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -1715,6 +1715,9 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = { static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { .halt_reg = 0x8a004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x8a004, + .hwcg_bit = 1, .clkr = { .enable_reg = 0x8a004, .enable_mask = BIT(0),