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Thu, 30 Jul 2020 15:37:29 -0500 From: Nicholas Kazlauskas To: , Subject: [PATCH 2/7] drm/amd/display: Reset plane when tiling flags change Date: Thu, 30 Jul 2020 16:36:37 -0400 Message-ID: <20200730203642.17553-3-nicholas.kazlauskas@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200730203642.17553-1-nicholas.kazlauskas@amd.com> References: <20200730203642.17553-1-nicholas.kazlauskas@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ce1fe0fe-3422-4e0f-01c0-08d834c86324 X-MS-TrafficTypeDiagnostic: DM5PR12MB2408: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qo8xm47dsBOVgYmpJkyOLksMxM0LdCoStUlfZyxaqUcQzch4ixodygxhCErTD2lpQRDJ976ajzN7/UEadJvlJWqHzkVMGnVt3FS6ER5lkSFdnM5msM0IRYq58AftKFhEihdVJT7qsj9l2rsXuWfKtcgm+5/0GQazf4OWh8LOp39e8XEJkzwxgr/8Ig5j1OU188mEmFKBhALN3wPjBRaR7xjWf3pSJa8MoJsvYscQXgh3CfNr39v8xVDxXvaBv/0kJDuhm6C2dw85rbjfp6se7wx0BHPWAEWi8vnl9HsgqJ81AvnHzw+vQzVPyNxsdmcjEC7nBXC4MqPTd84Q+EQD7MKEWWFhCBckvlmAMyNWePjUplk2FEVurf54THbVNZPwJdAwoPHj1ETZA+d3q/xCYw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SATLEXMB01.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFTY:; SFS:(4636009)(376002)(136003)(396003)(39860400002)(346002)(46966005)(356005)(70586007)(83380400001)(82310400002)(86362001)(2616005)(70206006)(426003)(44832011)(6666004)(186003)(1076003)(26005)(336012)(478600001)(4326008)(8936002)(8676002)(450100002)(316002)(54906003)(2906002)(82740400003)(81166007)(36756003)(47076004)(5660300002)(110136005); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2020 20:37:33.2713 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ce1fe0fe-3422-4e0f-01c0-08d834c86324 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB01.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2408 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hersen Wu , Rodrigo Siqueira , Bhawanpreet Lakha , Nicholas Kazlauskas Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" [Why] Enabling or disable DCC or switching between tiled and linear formats can require bandwidth updates. They're currently skipping all DC validation by being treated as purely surface updates. [How] Treat tiling_flag changes (which encode DCC state) as a condition for resetting the plane. Cc: Bhawanpreet Lakha Cc: Rodrigo Siqueira Cc: Hersen Wu Signed-off-by: Nicholas Kazlauskas Reviewed-by: Hersen Wu Signed-off-by: Nicholas Kazlauskas Reviewed-by: Rodrigo Siqueira --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7cc5ab90ce13..bf1881bd492c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8332,6 +8332,8 @@ static bool should_reset_plane(struct drm_atomic_state *state, * TODO: Come up with a more elegant solution for this. */ for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { + struct dm_plane_state *old_dm_plane_state, *new_dm_plane_state; + if (other->type == DRM_PLANE_TYPE_CURSOR) continue; @@ -8342,9 +8344,20 @@ static bool should_reset_plane(struct drm_atomic_state *state, if (old_other_state->crtc != new_other_state->crtc) return true; - /* TODO: Remove this once we can handle fast format changes. */ - if (old_other_state->fb && new_other_state->fb && - old_other_state->fb->format != new_other_state->fb->format) + /* Framebuffer checks fall at the end. */ + if (!old_other_state->fb || !new_other_state->fb) + continue; + + /* Pixel format changes can require bandwidth updates. */ + if (old_other_state->fb->format != new_other_state->fb->format) + return true; + + old_dm_plane_state = to_dm_plane_state(old_other_state); + new_dm_plane_state = to_dm_plane_state(new_other_state); + + /* Tiling and DCC changes also require bandwidth updates. */ + if (old_dm_plane_state->tiling_flags != + new_dm_plane_state->tiling_flags) return true; }