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Thu, 30 Jul 2020 15:37:30 -0500 From: Nicholas Kazlauskas To: , Subject: [PATCH 4/7] drm/amd/display: Use validated tiling_flags and tmz_surface in commit_tail Date: Thu, 30 Jul 2020 16:36:39 -0400 Message-ID: <20200730203642.17553-5-nicholas.kazlauskas@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200730203642.17553-1-nicholas.kazlauskas@amd.com> References: <20200730203642.17553-1-nicholas.kazlauskas@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e7d34c66-204a-4b09-f12d-08d834c8629e X-MS-TrafficTypeDiagnostic: BN6PR1201MB0116: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zbhyhPLIcTrklb7Dv3ggWOHRTb4+tH00Nj8IAmWWtyQFBFrh9GkCqCxEJQre2cD4UCLc66Lmv7HGRAIqZjjXw6AIYp2GPmdptf8LiPcgjLkNz4uaOjz1AwsA8rYTG0/aQhnwRvW0D062QiqdtoVTVEll3FF4zbntkz95cQZygAnvIdmfg2UN8/e36oLJsuGU7D99C6+nCasnA4sOE/NAGlybKF6PXftZu1JCvUB1CO+td99LQpHTjmPjvmWNEemen5fQRLWIcT8kDHbxTof0/haSDBfZpWR/wvEh52BMjwoqTWdkWedQJCfp2CvV7b12zKkB+y6Z2QROJ+MbBnkJ7YMERi4zGsc96iKCWYqS3ivBWFFshemmB4Svy7Gzdy04tJuYahwnAeeFvPhjovUnXQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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[How] These flags are now stored on dm_plane_state itself and acquried and validated during commit_check, so just use those instead. Cc: Daniel Vetter Cc: Bhawanpreet Lakha Cc: Rodrigo Siqueira Signed-off-by: Nicholas Kazlauskas Reviewed-by: Rodrigo Siqueira --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f78c09c9585e..0d5f45742bb5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7094,8 +7094,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, long r; unsigned long flags; struct amdgpu_bo *abo; - uint64_t tiling_flags; - bool tmz_surface = false; uint32_t target_vblank, last_flip_vblank; bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); bool pflip_present = false; @@ -7179,20 +7177,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, if (unlikely(r <= 0)) DRM_ERROR("Waiting for fences timed out!"); - /* - * We cannot reserve buffers here, which means the normal flag - * access functions don't work. Paper over this with READ_ONCE, - * but maybe the flags are invariant enough that not even that - * would be needed. - */ - tiling_flags = READ_ONCE(abo->tiling_flags); - tmz_surface = READ_ONCE(abo->flags) & AMDGPU_GEM_CREATE_ENCRYPTED; - fill_dc_plane_info_and_addr( - dm->adev, new_plane_state, tiling_flags, + dm->adev, new_plane_state, + dm_new_plane_state->tiling_flags, &bundle->plane_infos[planes_count], - &bundle->flip_addrs[planes_count].address, tmz_surface, - false); + &bundle->flip_addrs[planes_count].address, + dm_new_plane_state->tmz_surface, false); DRM_DEBUG_DRIVER("plane: id=%d dcc_en=%d\n", new_plane_state->plane->index,