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Thu, 30 Jul 2020 15:37:31 -0500 From: Nicholas Kazlauskas To: , Subject: [PATCH 5/7] drm/amd/display: Reset plane for anything that's not a FAST update Date: Thu, 30 Jul 2020 16:36:40 -0400 Message-ID: <20200730203642.17553-6-nicholas.kazlauskas@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200730203642.17553-1-nicholas.kazlauskas@amd.com> References: <20200730203642.17553-1-nicholas.kazlauskas@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9c912bef-2eab-4e8b-ff6f-08d834c863fe X-MS-TrafficTypeDiagnostic: MW2PR12MB2570: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lsDqLDZUSLJDGFB6zyRUTAFcEra2UNyYF1IMnH5z7e7xvMgA/Iy7HfTWT/YTLFtLgFkwTYLzj1QNjCOWjHVhWWey3NI9YKuGkZjV2hB1XtAg/fgXFSn/UnhC2H87TRW35ycxB0bJUTWYbVFo/UD64WoA7u6SqKooFNirFQdysXoGb/nw0/or25pu3x0WnT0y2tPM4IGq5Y9hUl3MVfEM89606fWoEDk1BFYg9qEpPt+bICe4ZeXjvApjQbKKnHyL2xiF6cn4wqpIROk76MpV4sm2HQZMkKFZzjCw/MqNDDj8Ed/vmkJ2KMPNx8KBC7VHO6p7iT54BAwTF9j7MDUDXYm+mGC5m4TzxhNMXc7l+xvEbxMrUHRxpQMxj4kwATuT6uvizyMpIgkpN3bLaptYlA== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SATLEXMB01.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFTY:; SFS:(4636009)(376002)(39860400002)(346002)(396003)(136003)(46966005)(478600001)(8936002)(36756003)(316002)(86362001)(6666004)(1076003)(450100002)(4326008)(44832011)(83380400001)(2616005)(54906003)(186003)(70206006)(82740400003)(356005)(336012)(81166007)(15650500001)(47076004)(426003)(82310400002)(70586007)(2906002)(110136005)(5660300002)(8676002)(26005); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2020 20:37:34.7045 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9c912bef-2eab-4e8b-ff6f-08d834c863fe X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB01.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2570 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hersen Wu , Bhawanpreet Lakha , Nicholas Kazlauskas Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" [Why] MEDIUM or FULL updates can require global validation or affect bandwidth. By treating these all simply as surface updates we aren't actually passing this through DC global validation. [How] There's currently no way to pass surface updates through DC global validation, nor do I think it's a good idea to change the interface to accept these. DC global validation itself is currently stateless, and we can move our update type checking to be stateless as well by duplicating DC surface checks in DM based on DRM properties. We wanted to rely on DC automatically determining this since DC knows best, but DM is ultimately what fills in everything into DC plane state so it does need to know as well. There are basically only three paths that we exercise in DM today: 1) Cursor (async update) 2) Pageflip (fast update) 3) Full pipe programming (medium/full updates) Which means that anything that's more than a pageflip really needs to go down path #3. So this change duplicates all the surface update checks based on DRM state instead inside of should_reset_plane(). Next step is dropping dm_determine_update_type_for_commit and we no longer require the old DC state at all for global validation. Optimization can come later so we don't reset DC planes at all for MEDIUM udpates and avoid validation, but we might require some extra checks in DM to achieve this. Cc: Bhawanpreet Lakha Cc: Hersen Wu Signed-off-by: Nicholas Kazlauskas Reviewed-by: Hersen Wu Signed-off-by: Nicholas Kazlauskas Reviewed-by: Rodrigo Siqueira --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0d5f45742bb5..2cbb29199e61 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8336,6 +8336,31 @@ static bool should_reset_plane(struct drm_atomic_state *state, if (old_other_state->crtc != new_other_state->crtc) return true; + /* Src/dst size and scaling updates. */ + if (old_other_state->src_w != new_other_state->src_w || + old_other_state->src_h != new_other_state->src_h || + old_other_state->crtc_w != new_other_state->crtc_w || + old_other_state->crtc_h != new_other_state->crtc_h) + return true; + + /* Rotation / mirroring updates. */ + if (old_other_state->rotation != new_other_state->rotation) + return true; + + /* Blending updates. */ + if (old_other_state->pixel_blend_mode != + new_other_state->pixel_blend_mode) + return true; + + /* Alpha updates. */ + if (old_other_state->alpha != new_other_state->alpha) + return true; + + /* Colorspace changes. */ + if (old_other_state->color_range != new_other_state->color_range || + old_other_state->color_encoding != new_other_state->color_encoding) + return true; + /* Framebuffer checks fall at the end. */ if (!old_other_state->fb || !new_other_state->fb) continue;