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[109.252.170.211]) by smtp.gmail.com with ESMTPSA id c17sm1504450lfr.23.2020.08.13.17.07.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 17:07:10 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Subject: [PATCH v5 09/36] memory: tegra20-emc: Initialize MC timings Date: Fri, 14 Aug 2020 03:05:54 +0300 Message-Id: <20200814000621.8415-10-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814000621.8415-1-digetx@gmail.com> References: <20200814000621.8415-1-digetx@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Mon, 17 Aug 2020 07:06:11 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" We're going to add interconnect support to the EMC driver. Once this support will be added, the Tegra20 devfreq driver will no longer be able to use clk_round_rate(emc) for building up OPP table. It's quite handy that struct tegra_mc contains memory timings which could be used by the devfreq drivers instead of the clk rate-rounding. The tegra_mc timings are populated by the MC driver only for Tegra30+ SoCs, hence the Tegra20 EMC could populate timings by itself. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/tegra20-emc.c | 54 ++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index c1cad4ce6251..5bf75b316a2f 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -10,7 +10,7 @@ config TEGRA_MC config TEGRA20_EMC tristate "NVIDIA Tegra20 External Memory Controller driver" default y - depends on ARCH_TEGRA_2x_SOC + depends on TEGRA_MC && ARCH_TEGRA_2x_SOC help This driver is for the External Memory Controller (EMC) found on Tegra20 chips. The EMC controls the external DRAM on the board. diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 5aa3a1da2975..a02ffc09c39e 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -15,12 +15,15 @@ #include #include #include +#include #include #include #include #include +#include "mc.h" + #define EMC_INTSTATUS 0x000 #define EMC_INTMASK 0x004 #define EMC_DBG 0x008 @@ -650,6 +653,45 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) emc, &tegra_emc_debug_max_rate_fops); } +static int tegra_emc_init_mc_timings(struct tegra_emc *emc) +{ + struct tegra_mc_timing *timing; + struct platform_device *pdev; + struct device_node *np; + struct tegra_mc *mc; + unsigned int i; + + if (!emc->num_timings) + return 0; + + np = of_find_compatible_node(NULL, NULL, "nvidia,tegra20-mc-gart"); + if (!np) + return -ENOENT; + + pdev = of_find_device_by_node(np); + of_node_put(np); + if (!pdev) + return -ENOENT; + + mc = platform_get_drvdata(pdev); + if (!mc) + return -EPROBE_DEFER; + + /* shouldn't happen */ + WARN_ON(mc->num_timings); + WARN_ON(mc->timings); + + mc->timings = devm_kcalloc(emc->dev, emc->num_timings, sizeof(*timing), + GFP_KERNEL); + if (!mc->timings) + return -ENOMEM; + + for (i = 0; i < emc->num_timings; i++, mc->num_timings++) + mc->timings[i].rate = emc->timings[i].rate; + + return 0; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -721,6 +763,18 @@ static int tegra_emc_probe(struct platform_device *pdev) goto unset_cb; } + /* + * Only Tegra30+ SoCs are having Memory Controller timings initialized + * by the MC driver. For Tegra20 we need to populate the MC timings + * from here. The MC timings will be used by the Tegra20 devfreq driver. + */ + err = tegra_emc_init_mc_timings(emc); + if (err) { + dev_err(&pdev->dev, "failed to initialize mc timings: %d\n", + err); + goto unset_cb; + } + platform_set_drvdata(pdev, emc); tegra_emc_debugfs_init(emc);