From patchwork Wed Sep 9 18:58:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 11766903 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1DEF3698 for ; Thu, 10 Sep 2020 07:23:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 02F0B20809 for ; Thu, 10 Sep 2020 07:23:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 02F0B20809 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1D9166E26C; Thu, 10 Sep 2020 07:23:12 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-out.m-online.net (mail-out.m-online.net [IPv6:2001:a60:0:28:0:1:25:1]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2DE806ECA2 for ; Wed, 9 Sep 2020 18:58:19 +0000 (UTC) Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 4BmrrQ1Khcz1rsMj; Wed, 9 Sep 2020 20:58:14 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 4BmrrQ0BX8z1qtYL; Wed, 9 Sep 2020 20:58:14 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id 2F7AGEfP-Mrw; Wed, 9 Sep 2020 20:58:12 +0200 (CEST) X-Auth-Info: ZLqCzL4pY/kwc/bMcrfLGQI2HYQx6LTyAfMIIaz251Y= Received: from desktop.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Wed, 9 Sep 2020 20:58:12 +0200 (CEST) From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] [RFC] drm/stm: Prefer faster display pixel clock over slower ones Date: Wed, 9 Sep 2020 20:58:02 +0200 Message-Id: <20200909185802.106844-1-marex@denx.de> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 10 Sep 2020 07:22:25 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Alexandre Torgue , Philippe Cornu , dri-devel@lists.freedesktop.org, =?utf-8?q?Yannick_Fertr=C3=A9?= , Maxime Coquelin , Vincent Abriou , linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" If the delta between requested pixelclock and resulting pixelclock is larger than the delta between requested pixelclock and the next step in available pixelclock (limited to 10% of pixelclock to avoid too much out-of-specification operation), use the faster pixelclock. This fixes the condition where the resulting pixelclock is much slower than the lowest clock rate supported by the display, while the next available pixelclock are just slightly faster than the highest clock rate supported by the display. Using the lower clock rate leads e.g. to subtle artifacts barely visible on the display, like flickering pixels. Using slightly faster clock leads to no such effect. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Benjamin Gaignard Cc: Maxime Coquelin Cc: Philippe Cornu Cc: Vincent Abriou Cc: Yannick Fertré Cc: dri-devel@lists.freedesktop.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com --- drivers/gpu/drm/stm/ltdc.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 6e28f707092f..07c73079293c 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -507,6 +507,25 @@ static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, { struct ltdc_device *ldev = crtc_to_ltdc(crtc); int rate = mode->clock * 1000; + int rate_min = clk_round_rate(ldev->pixel_clk, rate); + int rate_max = clk_round_rate(ldev->pixel_clk, rate + (rate / 10)); + + /* + * If the delta between requested pixelclock and resulting pixelclock + * is larger than the delta between requested pixelclock and the next + * step in available pixelclock (limited to 10% of pixelclock to avoid + * too much out-of-specification operation), use the faster pixelclock. + * + * This fixes the condition where the resulting pixelclock is much + * slower than the lowest clock rate supported by the display, while + * the next available pixelclock are just slightly faster than the + * highest clock rate supported by the display. Using the lower clock + * rate leads e.g. to subtle artifacts barely visible on the display, + * like flickering pixels. Using slightly faster clock leads to no + * such effect. + */ + if (rate - rate_min > rate_max - rate) + rate = rate_max; if (clk_set_rate(ldev->pixel_clk, rate) < 0) { DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);