diff mbox series

[2/2] drm/dp: add a number of DP 2.0 DPCD definitions

Message ID 20200917105038.12313-2-jani.nikula@intel.com
State New, archived
Headers show
Series [1/2] drm/dp: add subheadings to DPCD address definitions | expand

Commit Message

Jani Nikula Sept. 17, 2020, 10:50 a.m. UTC
Prepare for future with DP 2.0 DPCD definitions, with a couple of
related drive-by cleanups. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 include/drm/drm_dp_helper.h | 52 ++++++++++++++++++++++++++++++++-----
 1 file changed, 45 insertions(+), 7 deletions(-)

Comments

kernel test robot Sept. 17, 2020, 4:10 p.m. UTC | #1
Hi Jani,

I love your patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on tegra-drm/drm/tegra/for-next drm-tip/drm-tip linus/master drm-exynos/exynos-drm-next v5.9-rc5 next-20200917]
[cannot apply to drm/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Jani-Nikula/drm-dp-add-subheadings-to-DPCD-address-definitions/20200917-185206
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: nds32-randconfig-p001-20200917 (attached as .config)
compiler: nds32le-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=nds32 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   In file included from drivers/gpu/drm/drm_crtc_helper_internal.h:31,
                    from drivers/gpu/drm/drm_crtc_helper.c:51:
>> include/drm/drm_dp_helper.h:640: warning: "DP_ADJUST_TX_FFE_PRESET_LANE0_MASK" redefined
     640 | # define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK  (0xf << 4)
         | 
   include/drm/drm_dp_helper.h:638: note: this is the location of the previous definition
     638 | # define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK  (0xf << 0)
         | 
>> include/drm/drm_dp_helper.h:641: warning: "DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT" redefined
     641 | # define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 4
         | 
   include/drm/drm_dp_helper.h:639: note: this is the location of the previous definition
     639 | # define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
         | 
--
   In file included from include/drm/drm_dp_mst_helper.h:26,
                    from drivers/gpu/drm/drm_dp_mst_topology.c:43:
>> include/drm/drm_dp_helper.h:640: warning: "DP_ADJUST_TX_FFE_PRESET_LANE0_MASK" redefined
     640 | # define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK  (0xf << 4)
         | 
   include/drm/drm_dp_helper.h:638: note: this is the location of the previous definition
     638 | # define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK  (0xf << 0)
         | 
>> include/drm/drm_dp_helper.h:641: warning: "DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT" redefined
     641 | # define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 4
         | 
   include/drm/drm_dp_helper.h:639: note: this is the location of the previous definition
     639 | # define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
         | 
   drivers/gpu/drm/drm_dp_mst_topology.c: In function 'drm_dp_send_query_stream_enc_status':
   drivers/gpu/drm/drm_dp_mst_topology.c:3261:6: warning: variable 'len' set but not used [-Wunused-but-set-variable]
    3261 |  int len, ret;
         |      ^~~
--
   In file included from drivers/gpu/drm/bridge/analogix/analogix_dp_core.h:13,
                    from drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c:17:
>> include/drm/drm_dp_helper.h:640: warning: "DP_ADJUST_TX_FFE_PRESET_LANE0_MASK" redefined
     640 | # define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK  (0xf << 4)
         | 
   include/drm/drm_dp_helper.h:638: note: this is the location of the previous definition
     638 | # define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK  (0xf << 0)
         | 
>> include/drm/drm_dp_helper.h:641: warning: "DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT" redefined
     641 | # define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 4
         | 
   include/drm/drm_dp_helper.h:639: note: this is the location of the previous definition
     639 | # define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
         | 
   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c:527:5: warning: no previous prototype for 'analogix_dp_start_aux_transaction' [-Wmissing-prototypes]
     527 | int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
         |     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c:571:5: warning: no previous prototype for 'analogix_dp_write_byte_to_dpcd' [-Wmissing-prototypes]
     571 | int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
         |     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

# https://github.com/0day-ci/linux/commit/ee700fcadff2b9f1f941cd4af77242e51a139649
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Jani-Nikula/drm-dp-add-subheadings-to-DPCD-address-definitions/20200917-185206
git checkout ee700fcadff2b9f1f941cd4af77242e51a139649
vim +/DP_ADJUST_TX_FFE_PRESET_LANE0_MASK +640 include/drm/drm_dp_helper.h

   636	
   637	/* DP 2.0 128b/132b Link Layer */
   638	# define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK  (0xf << 0)
   639	# define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
 > 640	# define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK  (0xf << 4)
 > 641	# define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 4
   642	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff mbox series

Patch

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 3d9900e7d57c..6144a4c54e4f 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -123,6 +123,7 @@ 
 
 #define DP_MAX_DOWNSPREAD                   0x003
 # define DP_MAX_DOWNSPREAD_0_5		    (1 << 0)
+# define DP_STREAM_REGENERATION_STATUS_CAP  (1 << 1) /* 2.0 */
 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING  (1 << 6)
 # define DP_TPS4_SUPPORTED                  (1 << 7)
 
@@ -140,6 +141,7 @@ 
 
 #define DP_MAIN_LINK_CHANNEL_CODING         0x006
 # define DP_CAP_ANSI_8B10B		    (1 << 0)
+# define DP_CAP_ANSI_128B132B               (1 << 1) /* 2.0 */
 
 #define DP_DOWN_STREAM_PORT_COUNT	    0x007
 # define DP_PORT_COUNT_MASK		    0x0f
@@ -183,8 +185,14 @@ 
 #define DP_FAUX_CAP			    0x020   /* 1.2 */
 # define DP_FAUX_CAP_1			    (1 << 0)
 
+#define DP_SINK_VIDEO_FALLBACK_FORMATS      0x020   /* 2.0 */
+# define DP_FALLBACK_1024x768_60HZ_24BPP    (1 << 0)
+# define DP_FALLBACK_1280x720_60HZ_24BPP    (1 << 1)
+# define DP_FALLBACK_1920x1080_60HZ_24BPP   (1 << 2)
+
 #define DP_MSTM_CAP			    0x021   /* 1.2 */
 # define DP_MST_CAP			    (1 << 0)
+# define DP_SINGLE_STREAM_SIDEBAND_MSG      (1 << 1) /* 2.0 */
 
 #define DP_NUMBER_OF_AUDIO_ENDPOINTS	    0x022   /* 1.2 */
 
@@ -415,6 +423,9 @@ 
 # define DP_LINK_BW_2_7			    0x0a
 # define DP_LINK_BW_5_4			    0x14    /* 1.2 */
 # define DP_LINK_BW_8_1			    0x1e    /* 1.4 */
+# define DP_LINK_BW_10                      0x01    /* 2.0 128b/132b Link Layer */
+# define DP_LINK_BW_13_5                    0x04    /* 2.0 128b/132b Link Layer */
+# define DP_LINK_BW_20                      0x02    /* 2.0 128b/132b Link Layer */
 
 #define DP_LANE_COUNT_SET	            0x101
 # define DP_LANE_COUNT_MASK		    0x0f
@@ -466,12 +477,15 @@ 
 # define DP_TRAIN_PRE_EMPHASIS_SHIFT	    3
 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
 
+# define DP_TX_FFE_PRESET_VALUE_MASK        (0xf << 0) /* 2.0 128b/132b Link Layer */
+
 #define DP_DOWNSPREAD_CTRL		    0x107
 # define DP_SPREAD_AMP_0_5		    (1 << 4)
 # define DP_MSA_TIMING_PAR_IGNORE_EN	    (1 << 7) /* eDP */
 
 #define DP_MAIN_LINK_CHANNEL_CODING_SET	    0x108
 # define DP_SET_ANSI_8B10B		    (1 << 0)
+# define DP_SET_ANSI_128B132B               (1 << 1)
 
 #define DP_I2C_SPEED_CONTROL_STATUS	    0x109   /* DPI */
 /* bitmask as for DP_I2C_SPEED_CAP */
@@ -490,8 +504,19 @@ 
 # define DP_LINK_QUAL_PATTERN_ERROR_RATE    2
 # define DP_LINK_QUAL_PATTERN_PRBS7	    3
 # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM  4
-# define DP_LINK_QUAL_PATTERN_HBR2_EYE      5
-# define DP_LINK_QUAL_PATTERN_MASK	    7
+# define DP_LINK_QUAL_PATTERN_CP2520_PAT_1  5
+# define DP_LINK_QUAL_PATTERN_CP2520_PAT_2  6
+# define DP_LINK_QUAL_PATTERN_CP2520_PAT_3  7
+/* DP 2.0 UHBR10, UHBR13.5, UHBR20 */
+# define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08
+# define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10
+# define DP_LINK_QUAL_PATTERN_PRSBS9        0x18
+# define DP_LINK_QUAL_PATTERN_PRSBS11       0x20
+# define DP_LINK_QUAL_PATTERN_PRSBS15       0x28
+# define DP_LINK_QUAL_PATTERN_PRSBS23       0x30
+# define DP_LINK_QUAL_PATTERN_PRSBS31       0x38
+# define DP_LINK_QUAL_PATTERN_CUSTOM        0x40
+# define DP_LINK_QUAL_PATTERN_SQUARE        0x48
 
 #define DP_TRAINING_LANE0_1_SET2	    0x10f
 #define DP_TRAINING_LANE2_3_SET2	    0x110
@@ -594,9 +619,9 @@ 
 #define DP_LINK_STATUS_UPDATED		    (1 << 7)
 
 #define DP_SINK_STATUS			    0x205
-
-#define DP_RECEIVE_PORT_0_STATUS	    (1 << 0)
-#define DP_RECEIVE_PORT_1_STATUS	    (1 << 1)
+# define DP_RECEIVE_PORT_0_STATUS	    (1 << 0)
+# define DP_RECEIVE_PORT_1_STATUS	    (1 << 1)
+# define DP_STREAM_REGENERATION_STATUS      (1 << 2) /* 2.0 */
 
 #define DP_ADJUST_REQUEST_LANE0_1	    0x206
 #define DP_ADJUST_REQUEST_LANE2_3	    0x207
@@ -609,6 +634,12 @@ 
 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK   0xc0
 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6
 
+/* DP 2.0 128b/132b Link Layer */
+# define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK  (0xf << 0)
+# define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
+# define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK  (0xf << 4)
+# define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 4
+
 #define DP_ADJUST_REQUEST_POST_CURSOR2      0x20c
 # define DP_ADJUST_POST_CURSOR2_LANE0_MASK  0x03
 # define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
@@ -926,9 +957,8 @@ 
 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI       0x200e /* status same as 0x204 */
 #define DP_SINK_STATUS_ESI                     0x200f /* status same as 0x205 */
 
-/* Extended Receiver Capability */
+/* Extended Receiver Capability: See DP_DPCD_REV for definitions */
 #define DP_DP13_DPCD_REV                    0x2200
-#define DP_DP13_MAX_LINK_RATE               0x2201
 
 #define DP_DPRX_FEATURE_ENUMERATION_LIST    0x2210  /* DP 1.3 */
 # define DP_GTC_CAP					(1 << 0)  /* DP 1.3 */
@@ -940,6 +970,14 @@ 
 # define DP_VSC_EXT_CEA_SDP_SUPPORTED			(1 << 6)  /* DP 1.4 */
 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED		(1 << 7)  /* DP 1.4 */
 
+#define DP_128B132B_SUPPORTED_LINK_RATES       0x2215 /* 2.0 */
+# define DP_UHBR10                             (1 << 0)
+# define DP_UHBR20                             (1 << 1)
+# define DP_UHBR13_5                           (1 << 2)
+
+#define DP_128B132B_TRAINING_AUX_RD_INTERVAL   0x2216 /* 2.0 */
+# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
+
 /* Protocol Converter Extension */
 /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
 #define DP_CEC_TUNNELING_CAPABILITY            0x3000