From patchwork Mon Sep 21 11:02:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11789435 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9BCC66CA for ; Mon, 21 Sep 2020 11:29:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 80335207BC for ; Mon, 21 Sep 2020 11:29:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 80335207BC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 153096E287; Mon, 21 Sep 2020 11:29:11 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0868E6E282; Mon, 21 Sep 2020 11:28:46 +0000 (UTC) IronPort-SDR: JB/A3WT+PYBZHcYTngJGXLF6EpJisBv0KsaMayzTMLkiKEmDaFsGpiPGHLbnxHcuC4GdDdJlwI 3zPKOMOxW9dQ== X-IronPort-AV: E=McAfee;i="6000,8403,9750"; a="157738338" X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="157738338" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2020 04:28:45 -0700 IronPort-SDR: 8ZPLBd8QJx1EnEklOYkI2DI1Y1N/2zTEBGScDllvaP5WAdgbIU5whwsZmu+pDcJxbGvIxCrIqI z/ZmEIxlJvMw== X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="454009268" Received: from karthik-2012-client-platform.iind.intel.com ([10.223.74.217]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 21 Sep 2020 04:28:41 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Subject: [PATCH v11 5/8] drm/i915: Add dedicated plane hook for async flip case Date: Mon, 21 Sep 2020 16:32:07 +0530 Message-Id: <20200921110210.21182-6-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200921110210.21182-1-karthik.b.s@intel.com> References: <20200921110210.21182-1-karthik.b.s@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, Karthik B S , dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This hook is added to avoid writing other plane registers in case of async flips, so that we do not write the double buffered registers during async surface address update. v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville) -Add a vfunc for skl_program_async_surface_address and call it from intel_update_plane. (Ville) v8: -Rebased. v9: -Use if-else instead of return in intel_update_plane(). (Ville) -Rename 'program_async_surface_address' to 'async_flip'. (Ville) v10: -Check if async_flip hook is present before calling it. Otherwise it will OOPS during legacy cursor updates. (Ville) v11: -Rename skl_program_async_surface_address(). (Ville) Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni Reviewed-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_atomic_plane.c | 6 ++++- .../drm/i915/display/intel_display_types.h | 3 +++ drivers/gpu/drm/i915/display/intel_sprite.c | 24 +++++++++++++++++++ 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 79032701873a..6bd8e6cdd477 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -408,7 +408,11 @@ void intel_update_plane(struct intel_plane *plane, struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); trace_intel_update_plane(&plane->base, crtc); - plane->update_plane(plane, crtc_state, plane_state); + + if (crtc_state->uapi.async_flip && plane->async_flip) + plane->async_flip(plane, crtc_state, plane_state); + else + plane->update_plane(plane, crtc_state, plane_state); } void intel_disable_plane(struct intel_plane *plane, diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 3d4bf9b6a0a2..e3339e41ddf7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1183,6 +1183,9 @@ struct intel_plane { struct intel_plane_state *plane_state); int (*min_cdclk)(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); + void (*async_flip)(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state); }; struct intel_watermark_params { diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 76a3d9bfe0de..d4b8ba7e8015 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane, PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); } +static void +skl_plane_async_flip(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state) +{ + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + unsigned long irqflags; + enum plane_id plane_id = plane->id; + enum pipe pipe = plane->pipe; + u32 surf_addr = plane_state->color_plane[0].offset; + u32 plane_ctl = plane_state->ctl; + + plane_ctl |= skl_plane_ctl_crtc(crtc_state); + + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); + + intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), + intel_plane_ggtt_offset(plane_state) + surf_addr); + + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); +} + static void skl_program_plane(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, @@ -3095,6 +3118,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->get_hw_state = skl_plane_get_hw_state; plane->check_plane = skl_plane_check; plane->min_cdclk = skl_plane_min_cdclk; + plane->async_flip = skl_plane_async_flip; if (INTEL_GEN(dev_priv) >= 11) formats = icl_get_plane_formats(dev_priv, pipe,