From patchwork Thu Oct 8 09:31:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christian_K=C3=B6nig?= X-Patchwork-Id: 11822513 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C212D6CA for ; Thu, 8 Oct 2020 09:32:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 86B9821775 for ; Thu, 8 Oct 2020 09:32:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WmlB7YzZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 86B9821775 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E9426EA52; Thu, 8 Oct 2020 09:32:00 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-ed1-x542.google.com (mail-ed1-x542.google.com [IPv6:2a00:1450:4864:20::542]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0AC176EA4D for ; Thu, 8 Oct 2020 09:31:58 +0000 (UTC) Received: by mail-ed1-x542.google.com with SMTP id cq12so5133978edb.2 for ; Thu, 08 Oct 2020 02:31:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=2t52KS/isXXvxZNDg0mYu/AfCMI2KzEquq0kWMNynDA=; b=WmlB7YzZZ5oCVdBP89kYD38rjZCj8xAUcSwYP8kjVguz+I+2DgxmgHY3JwZmSleI8/ nO73SgblEabjOEfskEUKoe2DKY0SSKHdi0/FvmtOMRtJ+F9NGMvBo1zhmEYPRrpzUqjr UkS6gT/CLJ/41Yf/ask0mYBHUAjQ7YafQg5Rk5+70wlxiKKRchgFV+LsPqehp4UaU5Uk qcixsn28hyIdo0kHPTMh3HnD4qV/iOI6R5Xa6xvgMEbG1uTS2LgcGN/Wo7kfQA4B2kVJ TnlNNriVUq1DW49j7LDdId4q8ZkPIE1YZbgMClpeTFD5sKuz8kTcmCqFOzGYaQ1OI5Ru j2Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2t52KS/isXXvxZNDg0mYu/AfCMI2KzEquq0kWMNynDA=; b=XdFzJsa+fc+B5BzWyrJ7mT9d9yurVo41QHIQoHgfJrIklxoknwZSmjZ67j5n4IovYU 5o+CmcHTy0swG8zo4fN4Cs8uEKSszUM+cR5/h/ECyWYhPlj4CR2kEkLCJp+XzmJJT27P 4eYGICT8bejmcdfN6u5Cx8XaBkcrUrbd1F8s03U5YQA39rQxfYk5wxgE1zMsMYFSGp0Y 5BdGFJYOgKfiq9Nab0kpJKo7IAbI3J4BbtgHwHB5lfBJIdQMIMkXsM0t6/RwrqhujVss MCXPjhFrS2/yeKHiN79s4VqXqqy2p7q50ifJhHHIs6e8VV5VMV+hRPZMrk9mVzyXfZw7 qKyQ== X-Gm-Message-State: AOAM530owka0Yd4jPkHWrxJDioM/Q/tw82M1qWi8H4tViB7EsgSQt0Bm qhNQmhgbhg6D1O0xH7ls/DbMsEQtSMo= X-Google-Smtp-Source: ABdhPJzB6wvCcKQfn9Kr1i3HLpWlKTYQ0Fr2nQqelrgTmqXMDU/zOMtlATEXcJTUqLAIvfhMRPxrCA== X-Received: by 2002:a50:fc0b:: with SMTP id i11mr7774403edr.164.1602149516359; Thu, 08 Oct 2020 02:31:56 -0700 (PDT) Received: from abel.fritz.box ([2a02:908:1252:fb60:4c64:a9a0:5e0:905a]) by smtp.gmail.com with ESMTPSA id e2sm3649911ejd.81.2020.10.08.02.31.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Oct 2020 02:31:55 -0700 (PDT) From: " =?utf-8?q?Christian_K=C3=B6nig?= " X-Google-Original-From: =?utf-8?q?Christian_K=C3=B6nig?= To: dri-devel@lists.freedesktop.org, daniel@ffwll.ch Subject: [PATCH 2/4] drm/ttm: add caching state to ttm_bus_placement Date: Thu, 8 Oct 2020 11:31:52 +0200 Message-Id: <20201008093154.2991-2-christian.koenig@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201008093154.2991-1-christian.koenig@amd.com> References: <20201008093154.2991-1-christian.koenig@amd.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" And implement setting it up correctly in the drivers. This allows getting rid of the placement flags for this. Signed-off-by: Christian König Reviewed-by: Michael J. Ruhl --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 + drivers/gpu/drm/drm_gem_vram_helper.c | 1 + drivers/gpu/drm/nouveau/nouveau_bo.c | 11 +++++++++++ drivers/gpu/drm/qxl/qxl_ttm.c | 2 ++ drivers/gpu/drm/radeon/radeon_ttm.c | 2 ++ drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 1 + include/drm/ttm/ttm_resource.h | 8 +++++--- 7 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 7f41a47e7353..5b56a66063fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -769,6 +769,7 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso mem->bus.offset += adev->gmc.aper_base; mem->bus.is_iomem = true; + mem->bus.caching = ttm_write_combined; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c index ad58d0af5141..b9e7ce1adf25 100644 --- a/drivers/gpu/drm/drm_gem_vram_helper.c +++ b/drivers/gpu/drm/drm_gem_vram_helper.c @@ -981,6 +981,7 @@ static int bo_driver_io_mem_reserve(struct ttm_bo_device *bdev, case TTM_PL_VRAM: mem->bus.offset = (mem->start << PAGE_SHIFT) + vmm->vram_base; mem->bus.is_iomem = true; + mem->bus.caching = ttm_write_combined; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 0c0ca44a6802..cb878c0e8276 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1134,6 +1134,8 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *reg) struct nouveau_drm *drm = nouveau_bdev(bdev); struct nvkm_device *device = nvxx_device(&drm->client.device); struct nouveau_mem *mem = nouveau_mem(reg); + struct nvif_mmu *mmu = &drm->client.mmu; + const u8 type = mmu->type[drm->ttm.type_vram].type; int ret; mutex_lock(&drm->ttm.io_reserve_mutex); @@ -1149,6 +1151,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *reg) reg->bus.offset = (reg->start << PAGE_SHIFT) + drm->agp.base; reg->bus.is_iomem = !drm->agp.cma; + reg->bus.caching = ttm_write_combined; } #endif if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || @@ -1162,6 +1165,14 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *reg) reg->bus.offset = (reg->start << PAGE_SHIFT) + device->func->resource_addr(device, 1); reg->bus.is_iomem = true; + + /* Some BARs do not support being ioremapped WC */ + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && + type & NVIF_MEM_UNCACHED) + reg->bus.caching = ttm_uncached; + else + reg->bus.caching = ttm_write_combined; + if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { union { struct nv50_mem_map_v0 nv50; diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c index f50863493f64..61eb06dbbce8 100644 --- a/drivers/gpu/drm/qxl/qxl_ttm.c +++ b/drivers/gpu/drm/qxl/qxl_ttm.c @@ -83,11 +83,13 @@ int qxl_ttm_io_mem_reserve(struct ttm_bo_device *bdev, case TTM_PL_VRAM: mem->bus.is_iomem = true; mem->bus.offset = (mem->start << PAGE_SHIFT) + qdev->vram_base; + mem->bus.caching = ttm_cached; break; case TTM_PL_PRIV: mem->bus.is_iomem = true; mem->bus.offset = (mem->start << PAGE_SHIFT) + qdev->surfaceram_base; + mem->bus.caching = ttm_cached; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 130a7cea35c3..9b53a1d80632 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -372,6 +372,7 @@ static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso mem->bus.offset = (mem->start << PAGE_SHIFT) + rdev->mc.agp_base; mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; + mem->bus.caching = ttm_write_combined; } #endif break; @@ -382,6 +383,7 @@ static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso return -EINVAL; mem->bus.offset += rdev->mc.aper_base; mem->bus.is_iomem = true; + mem->bus.caching = ttm_write_combined; #ifdef __alpha__ /* * Alpha: use bus.addr to hold the ioremap() return, diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c index 1fa7f9438ec4..fae88969a15a 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c @@ -688,6 +688,7 @@ static int vmw_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resourc mem->bus.offset = (mem->start << PAGE_SHIFT) + dev_priv->vram_start; mem->bus.is_iomem = true; + mem->bus.caching = ttm_cached; break; default: return -EINVAL; diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h index 1b2f56163c6c..f48a70d39ac5 100644 --- a/include/drm/ttm/ttm_resource.h +++ b/include/drm/ttm/ttm_resource.h @@ -29,6 +29,7 @@ #include #include #include +#include #define TTM_MAX_BO_PRIORITY 4U @@ -148,9 +149,10 @@ struct ttm_resource_manager { * Structure indicating the bus placement of an object. */ struct ttm_bus_placement { - void *addr; - phys_addr_t offset; - bool is_iomem; + void *addr; + phys_addr_t offset; + bool is_iomem; + enum ttm_caching caching; }; /**