| Message ID | 20201025221735.3062-8-digetx@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce memory interconnect for NVIDIA Tegra SoCs | expand |
On Mon, Oct 26, 2020 at 01:16:50AM +0300, Dmitry Osipenko wrote: > The SoC core voltage can't be changed without taking into account the > clock rate of External Memory Controller. Document OPP table that will > be used for dynamic voltage frequency scaling, taking into account EMC > voltage requirement. Document optional core voltage regulator, which is > optional because some boards may have a fixed core regulator and still > frequency scaling may be desired to have. You need to document that property is optional in the binding. Best regards, Krzysztof > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > .../memory-controllers/nvidia,tegra20-emc.txt | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt > index 0a53adc6ccba..8d09b228ac42 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt > @@ -14,11 +14,23 @@ Properties: > - clocks : Should contain EMC clock. > - nvidia,memory-controller : Phandle of the Memory Controller node. > - #interconnect-cells : Should be 0. > +- core-supply: Phandle of voltage regulator of the SoC "core" power domain. > +- operating-points-v2: See ../bindings/opp/opp.txt for details. > > Child device nodes describe the memory settings for different configurations and clock rates. > > Example: > > + emc_icc_dvfs_opp_table: emc_opp_table0 { > + compatible = "operating-points-v2"; > + > + opp@36000000 { > + opp-microvolt = <950000 950000 1300000>; > + opp-hz = /bits/ 64 <36000000>; > + }; > + ... > + }; > + > memory-controller@7000f400 { > #address-cells = < 1 >; > #size-cells = < 0 >; > @@ -28,6 +40,8 @@ Example: > interrupts = <0 78 0x04>; > clocks = <&tegra_car TEGRA20_CLK_EMC>; > nvidia,memory-controller = <&mc>; > + core-supply = <&core_vdd_reg>; > + operating-points-v2 = <&emc_icc_dvfs_opp_table>; > } > > > -- > 2.27.0 >
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index 0a53adc6ccba..8d09b228ac42 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -14,11 +14,23 @@ Properties: - clocks : Should contain EMC clock. - nvidia,memory-controller : Phandle of the Memory Controller node. - #interconnect-cells : Should be 0. +- core-supply: Phandle of voltage regulator of the SoC "core" power domain. +- operating-points-v2: See ../bindings/opp/opp.txt for details. Child device nodes describe the memory settings for different configurations and clock rates. Example: + emc_icc_dvfs_opp_table: emc_opp_table0 { + compatible = "operating-points-v2"; + + opp@36000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <36000000>; + }; + ... + }; + memory-controller@7000f400 { #address-cells = < 1 >; #size-cells = < 0 >; @@ -28,6 +40,8 @@ Example: interrupts = <0 78 0x04>; clocks = <&tegra_car TEGRA20_CLK_EMC>; nvidia,memory-controller = <&mc>; + core-supply = <&core_vdd_reg>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; }
The SoC core voltage can't be changed without taking into account the clock rate of External Memory Controller. Document OPP table that will be used for dynamic voltage frequency scaling, taking into account EMC voltage requirement. Document optional core voltage regulator, which is optional because some boards may have a fixed core regulator and still frequency scaling may be desired to have. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- .../memory-controllers/nvidia,tegra20-emc.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+)