diff mbox series

drivers: amdgpu: amdgpu_display: Fixed the spelling of falg to flag

Message ID 20201109210725.24668-1-unixbhaskar@gmail.com (mailing list archive)
State New, archived
Headers show
Series drivers: amdgpu: amdgpu_display: Fixed the spelling of falg to flag | expand

Commit Message

Bhaskar Chowdhury Nov. 9, 2020, 9:07 p.m. UTC
s/falg/flag/p

Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--
2.26.2

Comments

Christian König Nov. 10, 2020, 11:56 a.m. UTC | #1
Am 09.11.20 um 22:07 schrieb Bhaskar Chowdhury:
> s/falg/flag/p
>
> Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>

Reviewed-by: Christian König <christian.koenig@amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 2e8a8b57639f..9223502c1e5b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -509,7 +509,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
>   	 * to avoid hang caused by placement of scanout BO in GTT on certain
>   	 * APUs. So force the BO placement to VRAM in case this architecture
>   	 * will not allow USWC mappings.
> -	 * Also, don't allow GTT domain if the BO doens't have USWC falg set.
> +	 * Also, don't allow GTT domain if the BO doens't have USWC flag set.
>   	 */
>   	if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
>   	    amdgpu_bo_support_uswc(bo_flags) &&
> --
> 2.26.2
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 2e8a8b57639f..9223502c1e5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -509,7 +509,7 @@  uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
 	 * to avoid hang caused by placement of scanout BO in GTT on certain
 	 * APUs. So force the BO placement to VRAM in case this architecture
 	 * will not allow USWC mappings.
-	 * Also, don't allow GTT domain if the BO doens't have USWC falg set.
+	 * Also, don't allow GTT domain if the BO doens't have USWC flag set.
 	 */
 	if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
 	    amdgpu_bo_support_uswc(bo_flags) &&