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Mon, 16 Nov 2020 09:37:58 -0800 (PST) Received: from dell.default ([91.110.221.159]) by smtp.gmail.com with ESMTPSA id 30sm16942828wrd.88.2020.11.16.09.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 09:37:57 -0800 (PST) From: Lee Jones To: lee.jones@linaro.org Subject: [PATCH 40/43] drm/radeon/cik: Move 'vce_v2_0_enable_mgcg()'s prototype to shared header Date: Mon, 16 Nov 2020 17:36:57 +0000 Message-Id: <20201116173700.1830487-41-lee.jones@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201116173700.1830487-1-lee.jones@linaro.org> References: <20201116173700.1830487-1-lee.jones@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, =?utf-8?q?Christian_K=C3=B6nig?= , linaro-mm-sig@lists.linaro.org, dri-devel@lists.freedesktop.org, Alex Deucher , linux-media@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/radeon/vce_v2_0.c:111:6: warning: no previous prototype for ‘vce_v2_0_enable_mgcg’ [-Wmissing-prototypes] 111 | void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable) | ^~~~~~~~~~~~~~~~~~~~ Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Sumit Semwal Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: linux-media@vger.kernel.org Cc: linaro-mm-sig@lists.linaro.org Signed-off-by: Lee Jones --- drivers/gpu/drm/radeon/cik.c | 2 +- drivers/gpu/drm/radeon/vce.h | 1 + drivers/gpu/drm/radeon/vce_v2_0.c | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 2af76463906ad..8b7a4f7b75766 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -41,6 +41,7 @@ #include "radeon_audio.h" #include "radeon_ucode.h" #include "si.h" +#include "vce.h" #define SH_MEM_CONFIG_GFX_DEFAULT \ ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) @@ -129,7 +130,6 @@ MODULE_FIRMWARE("radeon/mullins_rlc.bin"); MODULE_FIRMWARE("radeon/mullins_sdma.bin"); static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh); -extern void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable); static void cik_rlc_stop(struct radeon_device *rdev); static void cik_pcie_gen3_enable(struct radeon_device *rdev); static void cik_program_aspm(struct radeon_device *rdev); diff --git a/drivers/gpu/drm/radeon/vce.h b/drivers/gpu/drm/radeon/vce.h index 1eb4f5715202e..ccc9c00f0d02c 100644 --- a/drivers/gpu/drm/radeon/vce.h +++ b/drivers/gpu/drm/radeon/vce.h @@ -30,5 +30,6 @@ struct radeon_device; void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); +void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable); #endif /* __VCE_H__ */ diff --git a/drivers/gpu/drm/radeon/vce_v2_0.c b/drivers/gpu/drm/radeon/vce_v2_0.c index d6fde3659e65f..163c9bfc03da8 100644 --- a/drivers/gpu/drm/radeon/vce_v2_0.c +++ b/drivers/gpu/drm/radeon/vce_v2_0.c @@ -30,6 +30,7 @@ #include "radeon.h" #include "radeon_asic.h" #include "cikd.h" +#include "vce.h" #define VCE_V2_0_FW_SIZE (256 * 1024) #define VCE_V2_0_STACK_SIZE (64 * 1024)